发明申请
US20050139292A1 Method and apparatus for minimizing thickness-to-planarity and dishing in CMP 审中-公开
用于最小化CMP中的平坦度和凹陷的方法和装置

  • 专利标题: Method and apparatus for minimizing thickness-to-planarity and dishing in CMP
  • 专利标题(中): 用于最小化CMP中的平坦度和凹陷的方法和装置
  • 申请号: US10750734
    申请日: 2003-12-31
  • 公开(公告)号: US20050139292A1
    公开(公告)日: 2005-06-30
  • 发明人: Suresh Ramarajan
  • 申请人: Suresh Ramarajan
  • 主分类号: C23C8/02
  • IPC分类号: C23C8/02 C23C8/80
Method and apparatus for minimizing thickness-to-planarity and dishing in CMP
摘要:
The present technique is directed toward the fabrication of integrated circuits and provides for the hardening (modification) of a metal layer surface of a semiconductor wafer to reduce the amount of material removed during chemical mechanical planarization (CMP) of the metal layer. This hardening may be accomplished, for example, by oxidizing the metal surface and/or coating the metal surface with a polymer. In one implementation, a relatively thick and dense oxide layer is formed on the wafer metal surface prior to CMP, by injecting, for example, an oxidant, such as oxygen or ozone, near the end of an annealing cycle. Such hardening of the surface beneficially protects recessed regions from CMP chemical attack and CMP pad deformation, and thus reduces the thickness-to-planarity, dishing, and waste generation realized during CMP.
信息查询
0/0