A method for forming a metallic interconnect in a semiconductor device is disclosed. An example method forms an IDL on a substrate including predetermined devices, forms a via hole in the IDL, depositing a first metal diffusion preventive layer and a metal layer to form a via plug on the IDL, and performs a planarization process using the first metal diffusion preventive layer using as an etching stop layer. In addition, the example method forms a metallic interconnect on the first metal diffusion preventive layer, deposits the other metal diffusion preventive layer on the metallic interconnect, and etches a predetermined part of first and second metal diffusion preventive layers and the metallic interconnect using a mask pattern.