Provided is an on-chip serialized peripheral bus system and method of operating the same, wherein when a plurality of low-speed peripherals are connected to a system that employs a high-speed parallel bus, the existing parallel bus system for connecting the low-speed peripheral becomes serialized, thereby reducing a bus width of the parallel bus as well as improving a connection response time of the low-speed peripheral, and reducing a simultaneous transition frequency of the peripheral connection bus system to improve the performance of the overall system.