发明申请
- 专利标题: Apparatus and method for calculating a result of a modular multiplication
- 专利标题(中): 用于计算模数乘法的结果的装置和方法
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申请号: US10977561申请日: 2004-10-28
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公开(公告)号: US20050149595A1公开(公告)日: 2005-07-07
- 发明人: Wieland Fischer , Holger Sedlak , Jean-Pierre Seifert
- 申请人: Wieland Fischer , Holger Sedlak , Jean-Pierre Seifert
- 申请人地址: US DE Munich
- 专利权人: Infineon Technologies AG
- 当前专利权人: Infineon Technologies AG
- 当前专利权人地址: US DE Munich
- 优先权: DE10219158.1 20020429
- 主分类号: G06F7/53
- IPC分类号: G06F7/53 ; G06F7/72 ; G06F15/00
摘要:
Apparatus for calculating a result of a modular multiplication of a first operand and a second operand with regard to a modulus, each having a length of 2 n bits, the operands and the modulus are split into sub-operands of half the length and are fed to controller controlling MMD unit for performing a MultModDiv operation in accordance with a predetermined step sequence with corresponding input operands and MMD moduli to obtain integer quotient values and residual values with regard to the MMD modulus at an output. The combiner is operable to combine integer quotient values and residual values from predetermined steps of the step sequence to obtain the result.
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