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1.发明授权公开(公告)号：US07698357B2
公开(公告)日：2010-04-13
申请号：US11165834
申请日：2005-06-23
IPC分类号： G06F15/00
CPC分类号： G06F7/722
摘要： A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-ahead parameters using the approximated intermediate results. The first performer is further implemented to perform an exact three operand addition in the current iteration step using the exact intermediate result for the current iteration step and using the look-ahead parameters calculated for the current iteration step.
摘要翻译： 用于计算乘法器和乘法器的乘法的装置包括执行精确三个操作数相加的第一执行器和执行近似操作数相加的第二执行器，以及使用近似中间结果来计算当前先行参数的计算器。 第一执行者进一步实施，以在当前迭代步骤中使用当前迭代步骤的确切中间结果并使用为当前迭代步骤计算的预先参数来执行精确的三操作数添加。
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2.发明申请公开(公告)号：US20060064453A1
公开(公告)日：2006-03-23
申请号：US11165834
申请日：2005-06-23
IPC分类号： G06F7/52
CPC分类号： G06F7/722
摘要： A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-ahead parameters using the approximated intermediate results. The first performer is further implemented to perform an exact three operand addition in the current iteration step using the exact intermediate result for the current iteration step and using the look-ahead parameters calculated for the current iteration step.
摘要翻译： 用于计算乘法器和乘法器的乘法的装置包括执行精确三个操作数相加的第一执行器和执行近似操作数相加的第二执行器，以及使用近似中间结果来计算当前先行参数的计算器。 第一执行者进一步实施，以在当前迭代步骤中使用当前迭代步骤的确切中间结果并使用为当前迭代步骤计算的预先参数来执行精确的三操作数添加。
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3.发明申请公开(公告)号：US20050149595A1
公开(公告)日：2005-07-07
申请号：US10977561
申请日：2004-10-28
CPC分类号： G06F7/722 , G06F7/5324
摘要： Apparatus for calculating a result of a modular multiplication of a first operand and a second operand with regard to a modulus, each having a length of 2 n bits, the operands and the modulus are split into sub-operands of half the length and are fed to controller controlling MMD unit for performing a MultModDiv operation in accordance with a predetermined step sequence with corresponding input operands and MMD moduli to obtain integer quotient values and residual values with regard to the MMD modulus at an output. The combiner is operable to combine integer quotient values and residual values from predetermined steps of the step sequence to obtain the result.
摘要翻译： 用于计算关于模数的第一操作数和第二操作数的模乘结果的装置，每个模数具有2 n位的长度，操作数和模数被分割成长度的一半的子操作数，并被馈送 控制器控制MMD单元，用于根据具有相应输入操作数和MMD模数的预定步骤序列执行MultModDiv操作，以获得关于输出端的MMD模数的整数商值和残差值。 组合器可操作以从步骤序列的预定步骤组合整数商值和残差值以获得结果。
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4.发明授权Processor and method for a simultaneous execution of a calculation and a copying process 有权用于同时执行计算和复制过程的处理器和方法公开(公告)号：US07426529B2
公开(公告)日：2008-09-16
申请号：US11006519
申请日：2004-12-06
CPC分类号： G06F9/30014
摘要： A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in each cycle only one portion of the source register content is useable, a data bus connected to the source register, the destination register and the calculating unit, and a processor controller. The processor controller is operable to supply the source register content in portions to the calculating unit on the one hand and to the destination register on the other hand during the calculation via the data bus, so that after an execution of the calculation the source register content is written into the destination register. Therefore it is possible to obtain a register copy of a source register the destination register via a limited data bus without additional machine cycles for long operands to be processed in portions.
摘要翻译： 处理器包括具有源寄存器内容的源寄存器，目的地寄存器，用于使用源寄存器内容执行计算的计算单元，其中在几个计算周期中执行计算，并且其中在每个周期中，源的一部分 注册内容可用，连接到源寄存器，目的地寄存器和计算单元的数据总线以及处理器控制器。 处理器控制器可操作以在计算期间通过数据总线将源寄存器内容一部分提供给计算单元，另一方面提供给目标寄存器，使得在执行计算之后，源寄存器内容 被写入目的寄存器。 因此，有可能通过有限的数据总线获得源寄存器的寄存器副本，而不需要额外的机器周期来进行部分处理的长操作数。
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5.发明申请Processor and method for a simultaneous execution of a calculation and a copying process 有权用于同时执行计算和复制过程的处理器和方法公开(公告)号：US20050138337A1
公开(公告)日：2005-06-23
申请号：US11006519
申请日：2004-12-06
CPC分类号： G06F9/30014
摘要： A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in each cycle only one portion of the source register content is useable, a data bus connected to the source register, the destination register and the calculating unit, and a processor controller. The processor controller is operable to supply the source register content in portions to the calculating unit on the one hand and to the destination register on the other hand during the calculation via the data bus, so that after an execution of the calculation the source register content is written into the destination register. Therefore it is possible to obtain a register copy of a source register the destination register via a limited data bus without additional machine cycles for long operands to be processed in portions.
摘要翻译： 处理器包括具有源寄存器内容的源寄存器，目的地寄存器，用于使用源寄存器内容执行计算的计算单元，其中在几个计算周期中执行计算，并且其中在每个周期中，源的一部分 注册内容可用，连接到源寄存器，目的地寄存器和计算单元的数据总线以及处理器控制器。 处理器控制器可操作以在计算期间通过数据总线将源寄存器内容一部分提供给计算单元，另一方面提供给目标寄存器，使得在执行计算之后，源寄存器内容 被写入目的寄存器。 因此，有可能通过有限的数据总线获得源寄存器的寄存器副本，而不需要额外的机器周期来进行部分处理的长操作数。
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公开(公告)号：US20060010192A1
公开(公告)日：2006-01-12
申请号：US11166645
申请日：2005-06-23
IPC分类号： G06F7/52
CPC分类号： G06F7/722 , G06F7/5332
摘要： An apparatus for calculating a modular multiplication includes an examiner for examining digits of the multiplier with a lookahead algorithm to obtain a multiplication shift value. In addition, a determinator and intermediate-result shift value are provided which determine a positive intermediate-result shift value. A calculator for calculating a multiplicand shift value as the difference between the intermediate-result shift value and the multiplication shift value. The intermediate result from the preceding iteration step as well as the multiplicand are then shifted by the corresponding shifting magnitudes to then perform a three-operands addition with the shifted values, if need be while considering lookahead parameters.
摘要翻译： 用于计算模数乘法的装置包括用于利用前瞻算法检查乘数的数字以便获得乘法偏移值的检查者。 此外，提供确定正中间位移值的确定器和中间结果移位值。 计算器，用于计算被乘数位移值作为中间结果位移值与乘法偏移值之间的差值。 然后将前一迭代步骤的中间结果以及被乘数移位相应的移位量，然后如果需要考虑前瞻参数，则执行带有移位值的三操作数相加。
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公开(公告)号：US20050073346A1
公开(公告)日：2005-04-07
申请号：US10934301
申请日：2004-09-03
申请人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
发明人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
CPC分类号： G11C7/22 , G11C2207/007 , G11C2207/2227
摘要： A register cell includes a first input for a data unit to be written into the register cell. The register cell includes further a second input for a negated data unit to be written into the register cell. A first pair of oppositely coupled inverters as a first storage circuit is adapted to be coupled to the first input. A second pair of oppositely coupled inverters as a second storage circuit is adapted to be coupled to a second input. Using two oppositely coupled pairs of inverters makes it possible to initialize both the first input and the second input of the register either to a high voltage state (precharge) or to a low voltage state (discharge), such that the power consumption of the register cell is homogenized from one working clock to the next.
摘要翻译： 寄存器单元包括要写入寄存器单元的数据单元的第一输入。 寄存器单元还包括要被写入寄存器单元的否定数据单元的第二输入。 作为第一存储电路的第一对相反耦合的反相器适于耦合到第一输入。 作为第二存储电路的第二对相反耦合的反相器适于耦合到第二输入。 使用两个相对耦合的反相器对使得可以将寄存器的第一输入和第二输入初始化为高电压状态（预充电）或低电压状态（放电），使得寄存器的功耗 电池从一个工作时钟均匀化到下一个工作时钟。
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公开(公告)号：US07647367B2
公开(公告)日：2010-01-12
申请号：US11166645
申请日：2005-06-23
CPC分类号： G06F7/722 , G06F7/5332
摘要： An apparatus for calculating a modular multiplication includes an examiner for examining digits of the multiplier with a lookahead algorithm to obtain a multiplication shift value. In addition, a determinator and intermediate-result shift value are provided which determine a positive intermediate-result shift value. A calculator for calculating a multiplicand shift value as the difference between the intermediate-result shift value and the multiplication shift value. The intermediate result from the preceding iteration step as well as the multiplicand are then shifted by the corresponding shifting magnitudes to then perform a three-operands addition with the shifted values, if need be while considering lookahead parameters.
摘要翻译： 用于计算模数乘法的装置包括用于利用前瞻算法检查乘数的数字以便获得乘法偏移值的检查者。 此外，提供确定正中间位移值的确定器和中间结果移位值。 计算器，用于计算被乘数位移值作为中间结果位移值与乘法偏移值之间的差值。 然后将前一迭代步骤的中间结果以及被乘数移位相应的移位量，然后如果需要考虑前瞻参数，则执行带有移位值的三操作数相加。
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9.发明授权公开(公告)号：US07558817B2
公开(公告)日：2009-07-07
申请号：US10977561
申请日：2004-10-28
CPC分类号： G06F7/722 , G06F7/5324
摘要： Apparatus for calculating a result of a modular multiplication of a first operand and a second operand with regard to a modulus, each having a length of 2 n bits, the operands and the modulus are split into sub-operands of half the length and are fed to controller controlling MMD unit for performing a MultModDiv operation in accordance with a predetermined step sequence with corresponding input operands and MMD moduli to obtain integer quotient values and residual values with regard to the MMD modulus at an output. The combiner is operable to combine integer quotient values and residual values from predetermined steps of the step sequence to obtain the result.
摘要翻译： 用于计算关于模数的第一操作数和第二操作数的模乘结果的装置，每个模数具有2 n位的长度，操作数和模数被分割成长度的一半的子操作数，并被馈送 控制器控制MMD单元，用于根据具有相应输入操作数和MMD模数的预定步骤序列执行MultModDiv操作，以获得关于输出端的MMD模数的整数商值和残差值。 组合器可操作以从步骤序列的预定步骤组合整数商值和残差值以获得结果。
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公开(公告)号：US06999337B2
公开(公告)日：2006-02-14
申请号：US10934301
申请日：2004-09-03
申请人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
发明人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
IPC分类号： G11C11/00
CPC分类号： G11C7/22 , G11C2207/007 , G11C2207/2227
摘要： A register cell includes a first input for a data unit to be written into the register cell. The register cell includes further a second input for a negated data unit to be written into the register cell. A first pair of oppositely coupled inverters as a first storage circuit is adapted to be coupled to the first input. A second pair of oppositely coupled inverters as a second storage circuit is adapted to be coupled to a second input. Using two oppositely coupled pairs of inverters makes it possible to initialize both the first input and the second input of the register either to a high voltage state (precharge) or to a low voltage state (discharge), such that the power consumption of the register cell is homogenized from one working clock to the next.
摘要翻译： 寄存器单元包括要写入寄存器单元的数据单元的第一输入。 寄存器单元还包括要被写入寄存器单元的否定数据单元的第二输入。 作为第一存储电路的第一对相反耦合的反相器适于耦合到第一输入。 作为第二存储电路的第二对相反耦合的反相器适于耦合到第二输入。 使用两个相对耦合的反相器对使得可以将寄存器的第一输入和第二输入初始化为高电压状态（预充电）或低电压状态（放电），使得寄存器的功耗 电池从一个工作时钟均匀化到下一个工作时钟。
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