发明申请
US20050149777A1 Characterizing circuit performance by separating device and interconnect impact on signal delay
有权
通过分离器件和互连对信号延迟的影响来表征电路性能
- 专利标题： Characterizing circuit performance by separating device and interconnect impact on signal delay
- 专利标题（中）： 通过分离器件和互连对信号延迟的影响来表征电路性能
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申请号： US10742300申请日： 2003-12-18
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公开(公告)号： US20050149777A1公开(公告)日： 2005-07-07
- 发明人: Xiao-Jie Yuan , Michael Hart , Zicheng Ling , Steven Young
- 申请人： Xiao-Jie Yuan , Michael Hart , Zicheng Ling , Steven Young
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 主分类号： G01R31/28
- IPC分类号： G01R31/28 ; G01R31/3185 ; G01R31/3187 ; G11B5/00 ; G01R31/02 ; G06K5/04 ; G11B20/20
摘要：
An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
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