发明申请
US20050153498A1 Method of manufacturing p-channel MOS transistor and CMOS transistor
审中-公开
制造p沟道MOS晶体管和CMOS晶体管的方法
- 专利标题: Method of manufacturing p-channel MOS transistor and CMOS transistor
- 专利标题(中): 制造p沟道MOS晶体管和CMOS晶体管的方法
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申请号: US11020096申请日: 2004-12-27
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公开(公告)号: US20050153498A1公开(公告)日: 2005-07-14
- 发明人: Hak-Dong Kim
- 申请人: Hak-Dong Kim
- 申请人地址: KR Seoul
- 专利权人: DongbuAnam Semiconductor Inc.
- 当前专利权人: DongbuAnam Semiconductor Inc.
- 当前专利权人地址: KR Seoul
- 优先权: KR10-2003-0098380 20031227
- 主分类号: H01L21/225
- IPC分类号: H01L21/225 ; H01L21/265 ; H01L21/3115 ; H01L21/336 ; H01L21/8238 ; H01L29/10 ; H01L21/8234
摘要:
A method of manufacturing a p-channel MOS transistor including forming a structure by subsequently stacking gate insulating layer pattern and a gate conductive layer pattern on a semiconductor substrate. The method also includes forming first offset spacer layers on sides of the gate conductive layer pattern, forming a second-offset-spacer-layer insulating layer to cover the semiconductor substrate, the first offset spacer layer, and the gate conductive layer pattern, implanting p-type impurity ions in the second-offset-spacer-layer insulating layer by performing a first ion implanting process, and forming a second offset spacer layer and a gate spacer layer on the first offset spacer layer by performing a spacer layer forming process. The method further includes forming source/drain extension regions by diffusing the implanted p-type impurity ions by performing a thermal treatment process, and forming source/drain regions passing through the respective source/drain extension regions by performing a second ion implanting process by using the gate spacer layer as an ion implanting barrier.
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