公开(公告)号：US20080227265A1

公开(公告)日：2008-09-18

申请号：US12131016

申请日：2008-05-30

申请人： HAK DONG KIM

发明人： HAK DONG KIM

IPC分类号： H01L21/30

CPC分类号： H01L21/823481 ,  H01L21/823462

摘要： Methods of fabricating a gate-insulating layer of a dual-gate semiconductor device are disclosed. A disclosed method comprises sequentially forming a buffer oxide layer and a nitride layer on a semiconductor substrate having at least one high voltage device area and at least one low voltage device area; forming at least one trench by selectively removing at least one portion of the buffer oxide layer, the nitride layer and the semiconductor substrate; forming at least one device isolation layer by depositing an oxide layer in the trench and planarizing the oxide layer; removing the nitride layer and the buffer oxide layer remaining on the high voltage device area; forming a first gate-insulating layer on the high voltage device area; removing the nitride layer and the buffer oxide layer remaining on the low voltage device area; and forming a second gate-insulating layer on the low voltage device area.

摘要翻译： 公开了制造双栅极半导体器件的栅极绝缘层的方法。 所公开的方法包括在具有至少一个高电压器件面积和至少一个低电压器件面积的半导体衬底上依次形成缓冲氧化物层和氮化物层; 通过选择性地去除缓冲氧化物层，氮化物层和半导体衬底的至少一部分来形成至少一个沟槽; 通过在所述沟槽中沉积氧化物层并平坦化所述氧化物层来形成至少一个器件隔离层; 去除留在高电压装置区域上的氮化物层和缓冲氧化物层; 在所述高电压器件区域上形成第一栅极绝缘层; 去除残留在低压器件区域上的氮化物层和缓冲氧化物层; 以及在所述低电压器件区域上形成第二栅极绝缘层。

公开(公告)号：US07217627B2

公开(公告)日：2007-05-15

申请号：US10944316

申请日：2004-09-17

申请人： Hak-Dong Kim

发明人： Hak-Dong Kim

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/425

CPC分类号： H01L29/0847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/66575 ,  H01L29/78

摘要： The present disclosure provides an example of a semiconductor device. In addition, a method for fabricating a semiconductor device is outlined. The semiconductor device may be fabricated by providing a semiconductor substrate, forming a gate over the substrate, forming diffusion barrier ion regions, forming halo regions, forming a source, and forming a drain.

摘要翻译： 本公开提供了半导体器件的示例。 另外，概述了半导体器件的制造方法。 半导体器件可以通过提供半导体衬底，在衬底上形成栅极，形成扩散阻挡离子区域，形成晕区，形成源极和形成漏极来制造。

公开(公告)号：US20050142772A1

公开(公告)日：2005-06-30

申请号：US11023844

申请日：2004-12-27

申请人： Hak-Dong Kim

发明人： Hak-Dong Kim

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/10 ,  H01L21/8242 ,  H01L21/8236

CPC分类号： H01L29/105 ,  H01L21/28167

摘要： Provided is a method of manufacturing a semiconductor device capable of forming a thin high-quality gate oxide layer by suppressing occurrence of recoiled oxygen due to ion implanting. The method of manufacturing a semiconductor device includes steps of: removing an oxide layer from a semiconductor substrate; forming a well region in the substrate by performing a first ion implanting process; removing a native oxide layer from the substrate; adjusting a threshold voltage by performing a second ion implanting process on the substrate; and forming a gate oxide layer on the substrate.

摘要翻译： 提供一种制造半导体器件的方法，该半导体器件能够通过抑制由离子注入引起的反冲氧的发生而形成薄的高质量栅极氧化物层。 制造半导体器件的方法包括以下步骤：从半导体衬底去除氧化物层; 通过执行第一离子注入工艺在衬底中形成阱区; 从衬底去除原生氧化物层; 通过对所述基板执行第二离子注入处理来调整阈值电压; 以及在所述衬底上形成栅极氧化物层。

公开(公告)号：US20050153498A1

公开(公告)日：2005-07-14

申请号：US11020096

申请日：2004-12-27

申请人： Hak-Dong Kim

发明人： Hak-Dong Kim

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/2255 ,  H01L21/26586 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/1083 ,  H01L29/6656

摘要： A method of manufacturing a p-channel MOS transistor including forming a structure by subsequently stacking gate insulating layer pattern and a gate conductive layer pattern on a semiconductor substrate. The method also includes forming first offset spacer layers on sides of the gate conductive layer pattern, forming a second-offset-spacer-layer insulating layer to cover the semiconductor substrate, the first offset spacer layer, and the gate conductive layer pattern, implanting p-type impurity ions in the second-offset-spacer-layer insulating layer by performing a first ion implanting process, and forming a second offset spacer layer and a gate spacer layer on the first offset spacer layer by performing a spacer layer forming process. The method further includes forming source/drain extension regions by diffusing the implanted p-type impurity ions by performing a thermal treatment process, and forming source/drain regions passing through the respective source/drain extension regions by performing a second ion implanting process by using the gate spacer layer as an ion implanting barrier.

摘要翻译： 一种制造p沟道MOS晶体管的方法，包括通过在半导体衬底上堆叠栅极绝缘层图案和栅极导电层图案来形成结构。 该方法还包括在栅极导电层图案的侧面上形成第一偏移间隔层，形成第二偏移间隔层绝缘层以覆盖半导体衬底，第一偏移间隔层和栅极导电层图案，将p 通过执行第一离子注入工艺在第二偏移间隔层绝缘层中形成杂质离子，并且通过执行间隔层形成工艺在第一偏移间隔层上形成第二偏移间隔层和栅极间隔层。 该方法还包括通过进行热处理工艺扩散注入的p型杂质离子来形成源极/漏极延伸区域，以及通过使用第二离子注入工艺来形成通过相应的源极/漏极延伸区域的源极/漏极区域 栅间隔层作为离子注入屏障。

公开(公告)号：US20050142821A1

公开(公告)日：2005-06-30

申请号：US10998868

申请日：2004-11-29

申请人： Hak-Dong Kim

发明人： Hak-Dong Kim

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S438/923

摘要： Disclosed are methods of forming a halo region in n-channel type MOS (NMOS) transistors. In one example, the method includes forming, on a channel region of a semiconductor substrate, a structure having a gate insulation film pattern and a gate conductive film pattern stacked sequentially; forming an ion implantation buffer film on an exposed surface of the semiconductor substrate and the gate conductive film pattern; performing a first ion implantation process for injecting fluorine ions into the semiconductor substrate; performing a second ion implantation process for implanting p-type halo ions into the semiconductor substrate; performing a third ion implantation process for implanting n-type impurity ions into the semiconductor substrate; and diffusing the p-type halo ions and the n-type impurity ions using a thermal process.

摘要翻译： 公开了在n沟道型MOS（NMOS）晶体管中形成晕圈的方法。 在一个示例中，该方法包括在半导体衬底的沟道区上形成依次堆叠的具有栅极绝缘膜图案和栅极导电膜图案的结构; 在所述半导体衬底和所述栅极导电膜图案的暴露表面上形成离子注入缓冲膜; 执行用于将氟离子注入到半导体衬底中的第一离子注入工艺; 执行用于将p型卤素离子注入到所述半导体衬底中的第二离子注入工艺; 执行用于将n型杂质离子注入到半导体衬底中的第三离子注入工艺; 并使用热过程扩散p型卤素离子和n型杂质离子。

公开(公告)号：US20050142730A1

公开(公告)日：2005-06-30

申请号：US11020238

申请日：2004-12-27

申请人： Hak-Dong Kim

发明人： Hak-Dong Kim

IPC分类号： H01L27/092 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/8238

CPC分类号： H01L27/0688 ,  H01L21/84

摘要： In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper silicon layer in a second region, and then, a first insulating layer is formed to cover the first and second regions. Next, a silicon epitaxial layer is formed on the first insulating layer of the second region, and then, a p-channel MOS transistor is formed on the silicon epitaxial layer. An n-channel MOS transistor is formed on the upper silicon layer of the SOI substrate and a p-channel MOS transistor on the first insulating layer has a vertical step (relative to the n-channel MOS transistor), so that it is possible to increase integration degree.

摘要翻译： 在制造CMOS晶体管的方法中，在具有第一和第二区域的SOI衬底的第一区域中的上MOS晶体管上形成n沟道MOS晶体管。 接下来，通过去除第二区域中的上硅层来暴露SOI衬底的绝缘层，然后形成第一绝缘层以覆盖第一和第二区域。 接着，在第二区域的第一绝缘层上形成硅外延层，然后在硅外延层上形成p沟道MOS晶体管。 在SOI衬底的上硅层上形成n沟道MOS晶体管，并且第一绝缘层上的p沟道MOS晶体管具有垂直级（相对于n沟道MOS晶体管），因此可以 增加整合度。

公开(公告)号：US20050139911A1

公开(公告)日：2005-06-30

申请号：US11023104

申请日：2004-12-27

申请人： Hak-Dong Kim

发明人： Hak-Dong Kim

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/7833

摘要： A metal oxide semiconductor (MOS) transistor and a method of manufacturing the same are disclosed. An example MOS transistor includes a semiconductor substrate of a first conductivity type where an active region is defined, a gate insulating layer pattern and a gate formed on the active region of the substrate, a spacer formed on side walls of the gate, and source/drain extension regions of a second conductivity type formed within the substrate at both sides of the gate. The example MOS transistor further includes source/drain regions of the second conductivity type formed within the substrate at both side of the spacer and punch-through suppression regions of the first conductivity type formed within the active of the substrate. The punch-through suppression regions surround the source/drain extension regions and the source/drain regions under the gate.

摘要翻译： 公开了一种金属氧化物半导体（MOS）晶体管及其制造方法。 示例性MOS晶体管包括限定有源区的第一导电类型的半导体衬底，形成在衬底的有源区上的栅极绝缘层图案和栅极，形成在栅极的侧壁上的间隔物，以及源极/ 形成在栅极两侧的衬底内的第二导电类型的漏极延伸区域。 示例性MOS晶体管还包括形成在间隔物两侧的衬底内的第二导电类型的源极/漏极区域和形成在衬底的活性物质内的第一导电类型的穿通抑制区域。 穿通抑制区围绕栅极下的源极/漏极延伸区域和源极/漏极区域。

公开(公告)号：US07662210B2

公开(公告)日：2010-02-16

申请号：US11572298

申请日：2005-07-29

申请人： Young-Chul Kwon ,  Nam-Suk Hur ,  Young-Do Park ,  Hak-Dong Kim

发明人： Young-Chul Kwon ,  Nam-Suk Hur ,  Young-Do Park ,  Hak-Dong Kim

IPC分类号： C21B11/02 ,  C21B15/00

CPC分类号： C22B5/10 ,  C10J3/20 ,  C10J3/30 ,  C10J2200/152 ,  C10J2300/0903 ,  C10J2300/093 ,  C10J2300/0936 ,  C10J2300/0959 ,  C10J2300/16 ,  C10L5/10 ,  C10L5/14 ,  C10L5/361 ,  C21B13/002 ,  C21B13/0066 ,  C21B13/0073 ,  C21B13/14 ,  C21B2100/44 ,  Y02P10/136

摘要： The present invention relates to an apparatus for manufacturing molten irons by injecting fine carbonaceous materials into a melter-gasifier and a method for manufacturing molten irons using the same. The method for manufacturing molten irons according to the present invention includes steps of reducing mixtures containing iron ores in a reduction reactor and converting the mixtures containing iron ores into reduced materials, preparing lumped carbonaceous materials containing volatile matters as a heating source for melting the reduced materials, charging the lumped carbonaceous materials into a dome-shaped upper portion of a melter-gasifier and forming a coal packed bed, preparing fine carbonaceous materials containing volatile matters as a heating source for melting the reduced materials, injecting oxygen and the fine carbonaceous materials into the coal packed bed through a tuyere installed in the melter-gasifier, charging the reduced materials into the melter-gasifier connected to the reduction reactor and manufacturing molten irons, and supplying reducing gas in the melter-gasifier made from volatile matters contained both in the lumped carbonaceous materials and the fine carbonaceous materials to the reduction reactor.

摘要翻译： 本发明涉及一种通过将精细含碳材料注入到熔炉 - 气化器中来制造铁水的设备，以及使用该设备制造铁水的方法。 根据本发明的制造铁水的方法包括在还原反应器中还原含有铁矿石的混合物并将含有铁矿石的混合物转化为还原材料的步骤，制备含有挥发物质的集料含碳材料作为用于熔化还原材料的加热源 将集中的碳质材料装入熔炉 - 气化器的圆顶形上部并形成煤填充床，制备含有挥发物质的精细含碳材料作为用于熔化还原材料的加热源，将氧和细小的碳质材料注入 通过安装在熔化器 - 气化器中的风口将煤填充床装载到还原材料中，将其连接到还原反应器的熔炉 - 气化器中并制造铁水，并且在由包含两者的挥发性物质制成的熔化器 - 气化器中供应还原气体 集中的碳质材料和细小碳水化合物 颗粒材料到还原反应器。

公开(公告)号：US20070187757A1

公开(公告)日：2007-08-16

申请号：US11786168

申请日：2007-04-10

申请人： Hak-Dong Kim

发明人： Hak-Dong Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/66575 ,  H01L29/78

摘要： The present disclosure provides an example of a semiconductor device. In addition, a method for fabricating a semiconductor device is outlined. The semiconductor device may be fabricated by providing a semiconductor substrate, forming a gate over the substrate, forming diffusion barrier ion regions, forming halo regions, forming a source, and forming a drain.

摘要翻译： 本公开提供了半导体器件的示例。 另外，概述了半导体器件的制造方法。 半导体器件可以通过提供半导体衬底，在衬底上形成栅极，形成扩散阻挡离子区域，形成晕区，形成源极和形成漏极来制造。

公开(公告)号：US07223663B2

公开(公告)日：2007-05-29

申请号：US11022611

申请日：2004-12-27

申请人： Hak-Dong Kim

发明人： Hak-Dong Kim

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/6656 ,  H01L29/7833

摘要： MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.

摘要翻译： 公开了在它们的晕环区域和它们的源极/漏极延伸区域之间具有低结电容的MOS晶体管及其制造方法。 所公开的MOS晶体管包括：第一导电类型的半导体衬底; 栅极绝缘层图案和基板的有源区域上的栅极; 门的侧壁上的间隔物; 在栅极的相对侧的衬底内的第二导电类型的源极/漏极延伸区域，源极/漏极延伸区域具有渐变连接结构; 所述第一导电类型的卤素杂质区域在所述栅极的与所述源极/漏极延伸区域相邻的所述栅极的相对边缘之下; 以及衬底内的第二导电类型的源极/漏极区域在间隔物的相对侧上。