发明申请
- 专利标题: Boolean logic tree reduction circuit
- 专利标题(中): 布尔逻辑树缩减电路
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申请号: US10754665申请日: 2004-01-08
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公开(公告)号: US20050154771A1公开(公告)日: 2005-07-14
- 发明人: Fuk Ng , Liem Nguyen
- 申请人: Fuk Ng , Liem Nguyen
- 申请人地址: US MN Minneapolis
- 专利权人: MathStar, Inc.
- 当前专利权人: MathStar, Inc.
- 当前专利权人地址: US MN Minneapolis
- 主分类号: G06F7/00
- IPC分类号: G06F7/00 ; G06F17/50
摘要:
A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.
公开/授权文献
- US07002493B2 Boolean logic tree reduction circuit 公开/授权日:2006-02-21