公开(公告)号：US20060062036A1

公开(公告)日：2006-03-23

申请号：US10947877

申请日：2004-09-23

申请人： Fuk Ho Pius Ng ,  Y. Chiang

发明人： Fuk Ho Pius Ng ,  Y. Chiang

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： A reconfigurable state machine is provided. The state machine includes a current state register, for storing a current state, and at least one programmable state entry per state of the state machine. Each programmable entry includes a plurality of external signal inputs, a current state tag, at least one next state condition, and a respective next state output. A next state match circuit compares the current state with the current state tag and compares each of the next state conditions with at least one of the external signal inputs to produce a next state match output.

摘要翻译： 提供可重构状态机。 状态机包括用于存储当前状态的当前状态寄存器和每个状态机状态的至少一个可编程状态条目。 每个可编程项目包括多个外部信号输入，当前状态标签，至少一个下一个状态条件和相应的下一个状态输出。 下一状态匹配电路将当前状态与当前状态标签进行比较，并将下一状态条件中的每一个与至少一个外部信号输入进行比较，以产生下一状态匹配输出。

公开(公告)号：US20090144595A1

公开(公告)日：2009-06-04

申请号：US12023825

申请日：2008-01-31

申请人： Richard D. Reohr, JR. ,  Matthew F. Barr ,  Richard David Wiita

发明人： Richard D. Reohr, JR. ,  Matthew F. Barr ,  Richard David Wiita

IPC分类号： G01R31/3187 ,  G06F11/26 ,  G06F11/27

CPC分类号： G06F11/27 ,  G01R31/318519 ,  G01R31/3187

摘要： A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a controller. The array of objects is designed to operate at an operational clock speed during non-testing operation, wherein the design of the objects is not constrained to require within an object extra circuitry not essential to non-testing operation to facilitate built-in self-testing. The interfaces are connected to the objects to enable communication with the objects and to thereby facilitate built-in self-testing of the objects. The controller causes a selected subset of the objects to be activated and configured for testing, to stimulate the selected subset for some time with an input test pattern delivered via the interfaces while the selected subset of objects operates at the operational clock speed, and to observe a response of the selected subset of objects.

摘要翻译： 现场可编程对象阵列集成电路具有内置的自检功能。 集成电路包括可编程对象阵列，多个接口和控制器。 对象阵列被设计为在非测试操作期间以操作时钟速度操作，其中对象的设计不被限制为在物体内需要额外的电路，而不是非测试操作所必需的，以便于内置的自检 。 这些接口连接到对象，以实现与对象的通信，从而促进对象的内置自检。 控制器使得被选择的对象子集被激活并被配置用于测试，以通过接口递送的输入测试模式来刺激所选择的子集，同时所选择的对象子集以操作时钟速度操作，并观察 所选择的对象子集的响应。

公开(公告)号：US07353347B2

公开(公告)日：2008-04-01

申请号：US10947877

申请日：2004-09-23

申请人： Fuk Ho Pius Ng ,  Y. Paul Chiang

发明人： Fuk Ho Pius Ng ,  Y. Paul Chiang

IPC分类号： G06F12/00 ,  G06F7/38 ,  G11C15/00

CPC分类号： G11C15/00

摘要： A reconfigurable state machine is provided. The state machine includes a current state register, for storing a current state, and at least one programmable state entry per state of the state machine. Each programmable entry includes a plurality of external signal inputs, a current state tag, at least one next state condition, and a respective next state output. A next state match circuit compares the current state with the current state tag and compares each of the next state conditions with at least one of the external signal inputs to produce a next state match output.

摘要翻译： 提供可重构状态机。 状态机包括用于存储当前状态的当前状态寄存器和每个状态机状态的至少一个可编程状态条目。 每个可编程项目包括多个外部信号输入，当前状态标签，至少一个下一个状态条件和相应的下一个状态输出。 下一状态匹配电路将当前状态与当前状态标签进行比较，并将下一状态条件中的每一个与至少一个外部信号输入进行比较，以产生下一状态匹配输出。

公开(公告)号：US20060136531A1

公开(公告)日：2006-06-22

申请号：US10885205

申请日：2004-07-06

申请人： Fuk Ng

发明人： Fuk Ng

IPC分类号： G06F1/16

CPC分类号： G06F7/74

摘要： A method and apparatus are provided for aligning data in a binary word. A coded address is provided for each bit of the binary word. Each coded address is modified as a function of a logic state of the respective bit of the binary word to produce respective modified addresses. A shift control word is generated based on bit positions at which the modified addresses have a predetermined logic state. Bits in the binary word are shifted as a function of the shift control word to produce an aligned binary word.

摘要翻译： 提供了一种用于对齐二进制字中的数据的方法和装置。 为二进制字的每个位提供编码地址。 每个编码地址被修改为二进制字的相应位的逻辑状态的函数，以产生相应的修改的地址。 基于修改的地址具有预定逻辑状态的位位置生成移位控制字。 二进制字中的位作为移位控制字的函数移位以产生对齐的二进制字。

公开(公告)号：US20090206889A1

公开(公告)日：2009-08-20

申请号：US12032503

申请日：2008-02-15

申请人： Richard Reohr ,  Richard Wiita

发明人： Richard Reohr ,  Richard Wiita

IPC分类号： H03B19/00

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/3237 ,  Y02D10/126 ,  Y02D10/128

摘要： A method for ramping a high-speed clock to control power surge in an integrated circuit when transitioning from a low power holdstate to an operational state where the integrated circuit includes selected logic circuits adapted to be maintained in the holdstate. A core clock signal including a plurality of core clock pulses is gated with a ramping signal. The ramping signal includes a series of staged signals having gating pulses. Each staged signal is separated by a ramp interval, where the series of staged signals successively enables increasing numbers of clocking pulses from the core clock signal to be transmitted to a holdstate output until a predetermined operational core clock frequency is transmitted to the holdstate output bringing the integrated circuit to the operational state.

摘要翻译： 一种用于在从低功率保持状态转换到集成电路包括适于保持在保持状态中的选定逻辑电路的操作状态时，高速时钟斜坡上升以控制集成电路中的电力浪涌的方法。 包括多个核心时钟脉冲的核心时钟信号由斜坡信号选通。 斜坡信号包括具有门控脉冲的一系列分级信号。 每个分级信号以斜坡间隔分开，其中分级信号序列连续地使来自核心时钟信号的增加数量的时钟脉冲被发送到保持状态输出，直到将预定的操作核心时钟频率发送到保持状态输出， 集成电路到运行状态。

公开(公告)号：US20050154771A1

公开(公告)日：2005-07-14

申请号：US10754665

申请日：2004-01-08

申请人： Fuk Ng ,  Liem Nguyen

发明人： Fuk Ng ,  Liem Nguyen

IPC分类号： G06F7/00 ,  G06F17/50

CPC分类号： G06F7/00 ,  G06F17/505

摘要： A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.

摘要翻译： 提供了一种用于对具有多个位位置的多位二进制输入数据字的所有位执行布尔逻辑树函数的方法和装置。 每个位具有第一和第二互补逻辑状态之一。 通过将具有第一逻辑状态的输入数据字的所有位打包到经修改的数据字中的位置的第一连续集合中，并将具有第二逻辑状态的输入数据字的所有位组合成为第 经修改的数据字中的位位置的第二连续集合。 第一组和第二组中的位位数大于或等于零。 基于修改数据字中的第一和第二逻辑状态的模式生成布尔逻辑树函数的结果。

公开(公告)号：US20100020880A1

公开(公告)日：2010-01-28

申请号：US12492033

申请日：2009-06-25

申请人： Dean Stuart Susnow ,  Richard D. Reohr, JR.

发明人： Dean Stuart Susnow ,  Richard D. Reohr, JR.

IPC分类号： H04N7/26 ,  H03K19/177

CPC分类号： H04N19/433 ,  H03K19/17732 ,  H04N19/176 ,  H04N19/182 ,  H04N19/423 ,  H04N19/43 ,  H04N19/51 ,  H04N19/523 ,  H04N19/96

摘要： A field programmable object array integrated circuit has video data compression capability. The integrated circuit comprises an array of programmable objects and a video compression co-processor communicatively coupled to the array of objects. The video compression co-processor comprises a set of search engines and a subpixel engine. The subpixel engine can interpolate subpixels from integer pixels and shift the integer pixels by a predetermined number of subpixels. The search engines can perform a plurality of sum of absolute differences (SAD) computations between search window pixels and macroblock pixels to locate the best SAD value using either integer pixels and/or the interpolated subpixels.

摘要翻译： 现场可编程对象阵列集成电路具有视频数据压缩能力。 集成电路包括可编程对象的阵列和通信地耦合到对象阵列的视频压缩协处理器。 视频压缩协处理器包括一组搜索引擎和子像素引擎。 子像素引擎可以从整数像素内插子像素，并将整数像素移位预定数量的子像素。 搜索引擎可以在搜索窗口像素和宏块像素之间执行多个绝对差（SAD）和之和，以使用整数像素和/或内插子像素来定位最佳SAD值。

公开(公告)号：US20060080632A1

公开(公告)日：2006-04-13

申请号：US11042547

申请日：2005-01-25

申请人： Fuk Ho Ng ,  Liem Nguyen ,  David Trawick

发明人： Fuk Ho Ng ,  Liem Nguyen ,  David Trawick

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： An integrated circuit layout pattern is formed from a plurality of objects placed within the layout pattern. Each object has a homogenous communications interface, which is a rectilinear donut structure formed of communications elements surrounding a central object logic area. The communications elements are adapted to route data between the central object logic area and other rectilinear donut structures in the layout pattern.

摘要翻译： 从放置在布局图案内的多个物体形成集成电路布局图案。 每个对象具有均匀的通信接口，其是由围绕中心对象逻辑区域的通信元件形成的直线环形结构。 通信元件适于在布局图案中的中心对象逻辑区域和其它直线圆环结构之间路由数据。

公开(公告)号：US07002493B2

公开(公告)日：2006-02-21

申请号：US10754665

申请日：2004-01-08

申请人： Fuk Ho Pius Ng ,  Liem Thanh Nguyen

发明人： Fuk Ho Pius Ng ,  Liem Thanh Nguyen

IPC分类号： H03M7/00

CPC分类号： G06F7/00 ,  G06F17/505

摘要： A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.

摘要翻译： 提供了一种用于对具有多个位位置的多位二进制输入数据字的所有位执行布尔逻辑树函数的方法和装置。 每个位具有第一和第二互补逻辑状态之一。 通过将具有第一逻辑状态的输入数据字的所有位打包到经修改的数据字中的位置的第一连续集合中，并将具有第二逻辑状态的输入数据字的所有位组合成为第 经修改的数据字中的位位置的第二连续集合。 第一组和第二组中的位位数大于或等于零。 基于修改数据字中的第一和第二逻辑状态的模式生成布尔逻辑树函数的结果。

公开(公告)号：US20050228845A1

公开(公告)日：2005-10-13

申请号：US10822362

申请日：2004-04-12

申请人： Fuk Ho Pius Ng ,  Liem Thanh Nguyen

发明人： Fuk Ho Pius Ng ,  Liem Thanh Nguyen

IPC分类号： G06F7/52 ,  G06F7/53 ,  G06F7/533

CPC分类号： G06F7/5306 ,  G06F7/5338

摘要： A method and apparatus are provided for multiplying a multiplicand by a multiplier. The method and apparatus generate a plurality of partial products. Each partial product has a plurality of bits having respective binary weights, wherein each bit can have a first or second logic state. A first set of multiple-bit columns is formed from bits of the plurality of partial products, wherein the bits in each column of the first set have the same binary weight. Each multiple-bit column in the first set is encoded into a respective modified partial product, which represents a number of bits in the column having the first logic state. This process can be repeated until the number of partial products is reduces to a desired number.

摘要翻译： 提供了一种用于将被乘数乘以乘数的方法和装置。 该方法和装置产生多个部分积。 每个部分乘积具有多个具有相应二进制权重的比特，其中每个比特可以具有第一或第二逻辑状态。 第一组多位列由多个部分乘积的位形成，其中第一组的每列中的位具有相同的二进制权重。 第一集合中的每个多位列被编码成相应的修改的部分乘积，其表示具有第一逻辑状态的列中的位数。 该过程可以重复，直到部分产物的数量减少到所需数量。