A predetermined syncword detecting circuit includes a matched-bit-number comparing circuit, a comparing-result-change detecting circuit, a detected-result storing circuit, a total number detecting circuit, and a syncword detecting circuit. The matched-bit-number comparing circuit acquires a number of bits in a baseband signal that matches bits of the predetermined syncword and compares the number with a first threshold. The comparing-result-change detecting circuit samples the result of the matched-bit-number comparing circuit. The comparing-result-change detecting circuit detects changes in the result of the matched-bit-number comparing circuit. The detected-result storing circuit sequentially stores a result of the comparing-result-change detecting circuit. The total-number detecting circuit detects a total number of the result of the matched-bit-number comparing circuit. The result is included in an N cycle period and surpasses the first threshold. The syncword detecting circuit detects the predetermined syncword and selects an intermediate phase of the cycles as a detection phase.