发明申请
- 专利标题: Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby
- 专利标题(中): 使用选择性外延生长和部分平面化技术制造半导体集成电路的方法和由此制造的半导体集成电路
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申请号: US11065750申请日: 2005-02-24
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公开(公告)号: US20050184292A1公开(公告)日: 2005-08-25
- 发明人: Kun-Ho Kwak , Jae-Hoon Jang , Soon-Moon Jung , Won-Seok Cho , Hoon Lim , Sung-Jin Kim , Byung-Jun Hwang , Jong-Hyuk Kim
- 申请人: Kun-Ho Kwak , Jae-Hoon Jang , Soon-Moon Jung , Won-Seok Cho , Hoon Lim , Sung-Jin Kim , Byung-Jun Hwang , Jong-Hyuk Kim
- 申请人地址: KR Suwon-Si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-Si
- 优先权: KR2004-12400 20040224; KR2004-71886 20040908
- 主分类号: H01L21/8244
- IPC分类号: H01L21/8244 ; H01L27/108 ; H01L27/11
摘要:
Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.
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