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    Semiconductor integrated circuits with stacked node contact structures
    2.
    发明授权
    Semiconductor integrated circuits with stacked node contact structures 有权
    具有堆叠节点接触结构的半导体集成电路

    公开(公告)号：US07479673B2

    公开(公告)日：2009-01-20

    申请号：US11033432

    申请日：2005-01-11

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L27/02

    CPC分类号： H01L27/1214 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

    摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

    摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

    Semiconductor Integrated Circuits With Stacked Node Contact Structures
    3.
    发明申请
    Semiconductor Integrated Circuits With Stacked Node Contact Structures 审中-公开
    具有堆叠节点接触结构的半导体集成电路

    公开(公告)号：US20080023728A1

    公开(公告)日：2008-01-31

    申请号：US11868648

    申请日：2007-10-08

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L27/10

    CPC分类号： H01L27/1214 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

    摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

    摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

    METHODS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUITS USING SELECTIVE EPITAXIAL GROWTH AND PARTIAL PLANARIZATION TECHNIQUES AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY
    4.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUITS USING SELECTIVE EPITAXIAL GROWTH AND PARTIAL PLANARIZATION TECHNIQUES AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY 审中-公开
    使用选择性外延生长和部分平面化技术制造半导体集成电路的方法和半导体集成电路制造的方法

    公开(公告)号：US20070241335A1

    公开(公告)日：2007-10-18

    申请号：US11766655

    申请日：2007-06-21

    申请人： Kun-Ho KWAK ,  Jae-Hoon JANG ,  Soon-Moon JUNG ,  Won-Seok CHO ,  Hoon LIM ,  Sung-Jin KIM ,  Byung-Jun HWANG ,  Jong-Hyuk KIM

    发明人： Kun-Ho KWAK ,  Jae-Hoon JANG ,  Soon-Moon JUNG ,  Won-Seok CHO ,  Hoon LIM ,  Sung-Jin KIM ,  Byung-Jun HWANG ,  Jong-Hyuk KIM

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1108 ,  H01L27/11

    摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

    摘要翻译： 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

    Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques
    5.
    发明授权
    Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques 失效
    使用选择性外延生长和部分平面化技术制造半导体集成电路的方法

    公开(公告)号：US07247528B2

    公开(公告)日：2007-07-24

    申请号：US11065750

    申请日：2005-02-24

    申请人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

    发明人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1108 ,  H01L27/11

    摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

    摘要翻译： 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

    Methods of fabricating semiconductor devices having thin film transistors
    6.
    发明申请
    Methods of fabricating semiconductor devices having thin film transistors 有权
    制造具有薄膜晶体管的半导体器件的方法

    公开(公告)号：US20050221544A1

    公开(公告)日：2005-10-06

    申请号：US11098648

    申请日：2005-04-04

    申请人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

    发明人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

    IPC分类号： H01L21/00 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L29/15 ,  H01L29/786 ,  H01L31/0312

    CPC分类号： H01L27/1108 ,  H01L27/0688 ,  H01L27/11 ,  H01L29/78603

    摘要： Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

    摘要翻译： 提供制造半导体器件的方法。 层间绝缘层设置在单晶半导体衬底上。 提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。 模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。 使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。 在开口中设置单晶半导体区域。 单晶半导体区域包括单晶半导体外延图案的至少一部分。

    NAND flash memory device having a contact for controlling a well potential
    8.
    发明授权
    NAND flash memory device having a contact for controlling a well potential 失效
    具有用于控制阱电位的触点的NAND闪存器件

    公开(公告)号：US07723775B2

    公开(公告)日：2010-05-25

    申请号：US12314192

    申请日：2008-12-05

    申请人： Byung-jun Hwang ,  Jae-kwan Park ,  Jee-hoon Han ,  So-wi Jin ,  Nam-su Lim

    发明人： Byung-jun Hwang ,  Jae-kwan Park ,  Jee-hoon Han ,  So-wi Jin ,  Nam-su Lim

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines.

    摘要翻译： NAND闪速存储器件包括在衬底上沿第一方向延伸的多个有源区，所述有源区包括第一导电的第一阱，在与第一阱垂直的第二方向上在第一阱上延伸的多个字线 方向，第一和第二虚拟字线在第一阱上沿第二方向延伸，第一和第二虚拟字线彼此分离以限定它们之间的中间区域，第一和第二虚拟字线适于接收基本上 约0V的恒定偏置电压，以及在第一和第二伪字线之间的中间区域中的有源区域中的至少一个触点。

    NAND flash memory device having a contact for controlling a well potential
    9.
    发明申请
    NAND flash memory device having a contact for controlling a well potential 失效
    具有用于控制阱电位的触点的NAND闪存器件

    公开(公告)号：US20090152614A1

    公开(公告)日：2009-06-18

    申请号：US12314192

    申请日：2008-12-05

    申请人： Byung-jun Hwang ,  Jae-kwan Park ,  Jee-hoon Han ,  So-wi Jin ,  Nam-su Lim

    发明人： Byung-jun Hwang ,  Jae-kwan Park ,  Jee-hoon Han ,  So-wi Jin ,  Nam-su Lim

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines.

    摘要翻译： NAND闪速存储器件包括在衬底上沿第一方向延伸的多个有源区，所述有源区包括第一导电的第一阱，在与第一阱垂直的第二方向上在第一阱上延伸的多个字线 方向，第一和第二虚拟字线在第一阱上沿第二方向延伸，第一和第二虚拟字线彼此分离以限定它们之间的中间区域，第一和第二虚拟字线适于接收基本上 约0V的恒定偏置电压，以及在第一和第二伪字线之间的中间区域中的有源区域中的至少一个触点。

    Methods of forming semiconductor devices using an etch stop layer
    10.
    发明授权
    Methods of forming semiconductor devices using an etch stop layer 失效
    使用蚀刻停止层形成半导体器件的方法

    公开(公告)号：US07202180B2

    公开(公告)日：2007-04-10

    申请号：US10625452

    申请日：2003-07-23

    申请人： Kwang-Ok Koh ,  Kun-Ho Kwak ,  Byung-Jun Hwang ,  Han-Soo Kim

    发明人： Kwang-Ok Koh ,  Kun-Ho Kwak ,  Byung-Jun Hwang ,  Han-Soo Kim

    IPC分类号： H01L21/302

    CPC分类号： H01L29/6656 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/11 ,  H01L29/6659

    摘要： Methods of forming a semiconductor device are provided by forming a gate pattern that includes a gate electrode on a substrate. Lightly doped impurity diffusion layers are formed in the substrate at both sides of the gate pattern. Spacers are formed on sidewalls of the gate pattern. The spacers having a bottom width. Impurity ions are implanted using the gate pattern and the spacer as a mask to form a heavily doped impurity diffusion layer in the substrate. The spacers are removed. A conformal etch stop layer is formed on the gate pattern and the substrate. The etch stop layer is formed to a thickness of at least the bottom width of the spacers.

    摘要翻译： 通过在基板上形成包括栅电极的栅极图案来提供形成半导体器件的方法。 在栅极图案的两侧在衬底中形成轻掺杂杂质扩散层。 隔板形成在栅极图案的侧壁上。 间隔物具有底部宽度。 使用栅极图案和间隔物作为掩模注入杂质离子，以在衬底中形成重掺杂的杂质扩散层。 去除间隔物。 在栅极图案和衬底上形成保形蚀刻停止层。 蚀刻停止层形成为至少衬垫的底部宽度的厚度。