发明申请
US20050224921A1 Method for bonding wafers to produce stacked integrated circuits
审中-公开
用于接合晶片以产生堆叠集成电路的方法
- 专利标题: Method for bonding wafers to produce stacked integrated circuits
- 专利标题(中): 用于接合晶片以产生堆叠集成电路的方法
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申请号: US11150879申请日: 2005-06-09
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公开(公告)号: US20050224921A1公开(公告)日: 2005-10-13
- 发明人: Subhash Gupta , Paul Ho , Sangki Hong
- 申请人: Subhash Gupta , Paul Ho , Sangki Hong
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/48 ; H01L25/065 ; H01L29/40 ; H01L21/461
摘要:
An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit. In this case, the electrical conducting vias are also connected to various circuit elements by metallic conductors disposed in a dielectric layer that covers the circuit layer. A plurality of bonding pads are provided on one surface of the integrated circuit wafer. These pads may be part of the vias. These pads preferably extend above the surface of the integrated circuit wafer. A stacked integrated circuit according to the present invention is constructed by bonding two integrated circuit wafers together utilizing the bonding pads. One of the integrated circuit wafers is then thinned to a predetermined thickness determined by the depth of the vias by chemical/mechanical polishing (CMP) of the surface of that integrated circuit wafer that is not bonded to the other integrated circuit wafer, the stop layer in the vias preventing the CMP from removing wafer material that is within the first distance from the first surface of the substrate of the wafer being thinned.
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