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    Method for bonding wafers to produce stacked integrated circuits
    1.
    发明申请
    Method for bonding wafers to produce stacked integrated circuits 审中-公开
    用于接合晶片以产生堆叠集成电路的方法

    公开(公告)号：US20050224921A1

    公开(公告)日：2005-10-13

    申请号：US11150879

    申请日：2005-06-09

    申请人： Subhash Gupta ,  Paul Ho ,  Sangki Hong

    发明人： Subhash Gupta ,  Paul Ho ,  Sangki Hong

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L29/40 ,  H01L21/461

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

    摘要： An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit. In this case, the electrical conducting vias are also connected to various circuit elements by metallic conductors disposed in a dielectric layer that covers the circuit layer. A plurality of bonding pads are provided on one surface of the integrated circuit wafer. These pads may be part of the vias. These pads preferably extend above the surface of the integrated circuit wafer. A stacked integrated circuit according to the present invention is constructed by bonding two integrated circuit wafers together utilizing the bonding pads. One of the integrated circuit wafers is then thinned to a predetermined thickness determined by the depth of the vias by chemical/mechanical polishing (CMP) of the surface of that integrated circuit wafer that is not bonded to the other integrated circuit wafer, the stop layer in the vias preventing the CMP from removing wafer material that is within the first distance from the first surface of the substrate of the wafer being thinned.

    摘要翻译： 一种集成电路晶片元件和用于将其结合以产生堆叠集成电路的改进方法。 根据本发明的集成电路晶片包括具有由晶片材料构成的第一和第二表面的基板，所述第一表面具有包括在其上构成的集成电路元件的电路层。 多个通孔从第一表面延伸穿过电路层，并在离开第一表面的第一距离处终止在基板中。 通孔包括位于每个通孔底部的停止层，该停止层由比晶片材料更耐化学/机械抛光（CMP）的止动材料构成。 通孔可以填充有导电材料，以在堆叠集成电路中的各个电路层之间提供垂直连接。 在这种情况下，导电通孔也通过布置在覆盖电路层的电介质层中的金属导体连接到各种电路元件。 多个接合焊盘设置在集成电路晶片的一个表面上。 这些焊盘可以是通孔的一部分。 这些焊盘优选地在集成电路晶片的表面上方延伸。 根据本发明的堆叠集成电路是通过使用接合焊盘将两个集成电路晶片结合在一起而构成的。 然后通过化学/机械抛光（CMP）将集成电路晶片之一变薄到由通孔的深度确定的预定厚度，该集成电路晶片的表面未结合到另一集成电路晶片，停止层 在通孔中，防止CMP从晶片的衬底的第一表面的第一距离内移除晶片材料。

    Reversed damascene process for multiple level metal interconnects
    3.
    发明授权
    Reversed damascene process for multiple level metal interconnects 有权
    用于多级金属互连的反向镶嵌工艺

    公开(公告)号：US06352917B1

    公开(公告)日：2002-03-05

    申请号：US09598691

    申请日：2000-06-21

    申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

    发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

    IPC分类号： H01L214763

    CPC分类号： H01L21/76885 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.

    摘要翻译： 已经实现了在集成电路器件的制造中形成包含镶嵌互连和通孔插塞的金属互连级别的新方法。 该方法创建一个反向的双镶嵌结构。 第一电介质层设置在半导体衬底上。 图案化电介质层以形成用于计划的大马士革互连的沟槽。 可以可选地在沟槽侧壁上形成绝缘间隔物。 导电阻挡层沉积在电介质层上并衬在沟槽上。 沉积优选包含铜的金属层，覆盖在导电阻挡层上并填充沟槽。 金属层和导电阻挡层被抛光，从而形成镶嵌互连。 可以任选地沉积钝化层。 大马士革互连被图案化以形成覆盖大马士革互连的通孔塞。 图案化包括使用覆盖并保护大马士革互连部分的通孔掩模部分地蚀刻镶嵌互连。 在蚀刻过程中，沟槽掩模也覆盖并保护第一介电层免受金属污染。

    Selective etching of unreacted nickel after salicidation
    4.
    发明授权
    Selective etching of unreacted nickel after salicidation 有权
    腐蚀后对未反应的镍进行选择性蚀刻

    公开(公告)号：US06225202B1

    公开(公告)日：2001-05-01

    申请号：US09598689

    申请日：2000-06-21

    申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

    发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

    IPC分类号： H01L214763

    CPC分类号： H01L29/665 ,  C23F4/00 ,  H01L21/32136

    摘要： A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted. The unreacted nickel or cobalt layer is exposed to a plasma containing carbon monoxide gas wherein the carbon monoxide gas reacts with the unreacted nickel or cobalt thereby removing the unreacted nickel or cobalt from the substrate to complete salicidation of the integrated circuit device.

    摘要翻译： 描述了使用一氧化碳干燥汽提在硅化后除去未反应的镍或钴的方法。 在半导体衬底中形成浅沟槽隔离区域，该半导体衬底围绕并使活性区域与其它有源区域电隔离。 在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。 在栅极电极和相关的源极和漏极区域，浅沟槽隔离区域和介电间隔物上沉积镍或钴层。 半导体衬底被退火，由此将覆盖在栅电极和所述源极和漏极区域上的镍或钴层转变成镍或钴硅化物层，并且其中覆盖电介质间隔物和浅沟槽隔离区的镍或钴层是未反应的。 将未反应的镍或钴层暴露于含有一氧化碳气体的等离子体中，其中一氧化碳气体与未反应的镍或钴反应，从而从基板除去未反应的镍或钴，以完成集成电路器件的水化。

    Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
    9.
    发明授权
    Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene 有权
    复合硅 - 金属氮化物屏障，以防铜铜镶嵌中金属氟化物的形成

    公开(公告)号：US06372636B1

    公开(公告)日：2002-04-16

    申请号：US09587467

    申请日：2000-06-05

    申请人： Simon Chooi ,  Subhash Gupta ,  Mei-Sheng Zhou ,  Sangki Hong

    发明人： Simon Chooi ,  Subhash Gupta ,  Mei-Sheng Zhou ,  Sangki Hong

    IPC分类号： H01L214763

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76855

    摘要： A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure -single, dual, or multi-structure- is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer. In the third embodiment, the ternary metal silicon nitride spacer is formed by etching after having first formed the amorphous silicon layer and the nitride layer, in that order, and then etching the passivation/barrier layer at the bottom of the damascene structure into the underlying copper layer. In all three embodiments, metal nitride reacts with amorphous silicon to form a ternary metal silicon nitride having an excellent property of adhering to copper while at the same time for forming an excellent barrier to diffusion of copper.

    摘要翻译： 公开了一种形成非晶硅间隔物的方法，随后在铜镶嵌结构 - 单，双或多结构中在间隔物上形成金属氮化物，以防止在铜中形成氟化物。 在第一实施例中，通过在形成在内部的非晶硅间隔物上形成金属氮化物层之后，通过从双镶嵌结构形成开口到下面的铜层来形成铜镶嵌层和下面的铜金属层之间的互连 双镶嵌结构的墙壁。 在第二实施例中，通过在形成非晶硅间隔物之后并且在形成金属氮化物层之前通过蚀刻到下面的铜层中，由双镶嵌结构制造双镶嵌结构和下面的铜线之间的互连。 在第三实施例中，三元金属氮化硅间隔物依次先形成非晶硅层和氮化物层后，通过蚀刻形成，然后在镶嵌结构的底部蚀刻钝化/阻挡层，形成底层 铜层。 在所有三个实施例中，金属氮化物与非晶硅反应形成具有优异的粘附铜特性的三元金属氮化硅，同时形成对铜的扩散的优异屏障。