- 专利标题: Successive approximation analog/digital converter with reduced chip area
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申请号: US11151551申请日: 2005-06-14
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公开(公告)号: US20050231404A1公开(公告)日: 2005-10-20
- 发明人: Hisashi Harada , Takahiro Miki , Hideo Matsui
- 申请人: Hisashi Harada , Takahiro Miki , Hideo Matsui
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 优先权: JP2003-280922(P) 20030728
- 主分类号: H03M1/14
- IPC分类号: H03M1/14 ; H03M1/10 ; H03M1/12 ; H03M1/34 ; H03M1/46
摘要:
A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.
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