Invention Application
US20050232003A1 MRAM including unit cell formed of one transistor and two magnetic tunnel junctions (MTJs) and method for fabricating the same
有权
包括由一个晶体管和两个磁性隧道结(MTJ)形成的晶胞的MRAM及其制造方法
- Patent Title: MRAM including unit cell formed of one transistor and two magnetic tunnel junctions (MTJs) and method for fabricating the same
- Patent Title (中): 包括由一个晶体管和两个磁性隧道结(MTJ)形成的晶胞的MRAM及其制造方法
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Application No.: US11152346Application Date: 2005-06-15
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Publication No.: US20050232003A1Publication Date: 2005-10-20
- Inventor: Wan-jun Park , Hyung-soon Shin , Seung-jun Lee
- Applicant: Wan-jun Park , Hyung-soon Shin , Seung-jun Lee
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD
- Current Assignee Address: KR Suwon-si
- Priority: KR2003-3476 20030118
- Main IPC: H01L27/105
- IPC: H01L27/105 ; G11C11/15 ; H01L21/8246 ; H01L43/08 ; G11C11/00

Abstract:
In an MRAM and method for fabricating the same, the MRAM includes a semiconductor substrate, a transistor formed on the semiconductor substrate, an interlayer dielectric formed on the semiconductor substrate to cover the transistor, and first and second MTJ cells formed in the interlayer dielectric to be coupled in parallel with a drain region of the transistor, wherein the first MTJ cell is coupled to a first bit line formed in the interlayer dielectric and the second MTJ cell is coupled to a second bit line formed in the interlayer dielectric, and wherein a data line is formed between the first MTJ cell and a gate electrode of the transistor to be perpendicular to the first bit line and the second bit line. The MRAM provides high integration density, sufficient sensing margin, high-speed operation and reduced noise, requires reduced current for recording data and eliminates a voltage offset.
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