The present invention relates to a data output apparatus for a memory device, and more particularly to, a data output apparatus improved a data transferring speed by re-amplifying a data amplified by a bitline sense amplifier and transferring it to global input/output lines. The data output apparatus comprises: first and second local data lines for receiving data transferred from a pair of bitlines of a memory device; an amplifier interposed between the first and second local data lines; a first CMOS buffer means for receiving data on the first local data line; a second CMOS buffer means for receiving data on the second local data line; a first latch means for holding an output signal of the first CMOS buffer means; a second latch means for holding an output signal of the second CMOS buffer means; and a pull-up transistor and a pull-down transistor coupled between a driving voltage and a ground terminal in series. Here, an output signal of the first latch means is applied to a gate of the pull-up transistor, while an output signal of the second latch means is applied to the pull-down transistor.