A semiconductor memory device 1 comprises precharge circuits 31, 32 corresponding to global data line pairs DL0/NDL0, DL1/NDL1, but not a precharge circuit corresponding to a local data line pair LDL/NLDL. In a command waiting state, data line selection switches 21, 22 are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches 21, 22, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.