公开(公告)号：US07779277B2

公开(公告)日：2010-08-17

申请号：US11730683

申请日：2007-04-03

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： G06F1/00 ,  G11C29/00 ,  H02J1/00

CPC分类号： G11C29/12 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/1201

摘要： A semiconductor integrated circuit including on a single chip a plurality of circuit blocks and a plurality of internal power supply circuits for delivering a common supply voltage to the plurality of circuit blocks includes: a shared power supply interconnection for connecting the plurality of circuit blocks and the plurality of internal power supply circuits; and an external pad connected to the shared power supply interconnection. Whether or not each of the internal power supply circuits delivers the supply voltage is controlled by a certain power supply control signal.

摘要翻译： 包括在单个芯片上的多个电路块的半导体集成电路和用于向多个电路块传送公共电源电压的多个内部电源电路包括：用于连接多个电路块的共享电源互连和 多个内部电源电路; 以及连接到共享电源互连的外部焊盘。 每个内部电源电路的输出电源电压是否由一定的电源控制信号控制。

公开(公告)号：US07330386B2

公开(公告)日：2008-02-12

申请号：US11491934

申请日：2006-07-25

申请人： Naoki Kuroda ,  Masanobu Hirose

发明人： Naoki Kuroda ,  Masanobu Hirose

IPC分类号： G11C7/00

CPC分类号： G11C17/12 ,  G11C2207/2227

摘要： In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. During a stand-by period, each of the source lines is controlled to be in a state where the source bias potential is supplied and, during an active period, one or more of the source lines which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.

摘要翻译： 在存储单元阵列中，提供源极线，使得源极线中的每一个连接到属于相邻两行的存储单元中的每一个，以及用于提供高于地的源极偏置电位的多个源极偏置控制电路 提供电位并且低于电源电位以分别对应于源极线。 在待机期间，每个源极线被控制为处于源极偏置电位被提供的状态，并且在有效周期期间，一个或多个不连接到存储器单元之一的源极线 被读取的数据被控制为处于提供源极偏置电位的状态。

公开(公告)号：US20070030744A1

公开(公告)日：2007-02-08

申请号：US11487976

申请日：2006-07-18

申请人： Toshihiro Nakamura ,  Naoki Kuroda ,  Masanobu Hirose

发明人： Toshihiro Nakamura ,  Naoki Kuroda ,  Masanobu Hirose

IPC分类号： G11C7/00

CPC分类号： H01L27/0207 ,  H01L27/105

摘要： Source potential connection transistors, each supplying a source control potential from a source potential wiring to a source node, are disposed so as to be dispersed in a memory cell array. In addition, a source potential control circuit is disposed inside a row decoder block. With this configuration, the number of the cells connected to each word line can be increased, and the area of the memory core can be reduced. Furthermore, the pattern shape of the diffusion layer constituting the source potential connection transistor is made the same as that of the diffusion layer of a memory cell transistor, whereby mask creation can be facilitated.

摘要翻译： 源电位连接晶体管，每个源极控制电位从源极布线提供到源极节点，以分散在存储单元阵列中。 此外，源电位控制电路设置在行解码器块内。 利用这种配置，可以增加连接到每个字线的单元的数量，并且可以减小存储器核心的面积。 此外，构成源极电位连接晶体管的扩散层的图案形状与存储单元晶体管的扩散层的图案形状相同，从而可以促进掩模创建。

公开(公告)号：US20060250869A1

公开(公告)日：2006-11-09

申请号：US11484756

申请日：2006-07-12

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C2207/002

摘要： A semiconductor memory device 1 comprises precharge circuits 31, 32 corresponding to global data line pairs DL0/NDL0, DL1/NDL1, but not a precharge circuit corresponding to a local data line pair LDL/NLDL. In a command waiting state, data line selection switches 21, 22 are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches 21, 22, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.

摘要翻译： 半导体存储器件1包括对应于全局数据线对DL 0 / NDL 0，DL 1 / NDL 1的预充电电路31,32，而不是与本地数据线对LDL / NLDL相对应的预充电电路。 在命令等待状态下，数据线选择开关21,22被控制为处于连接状态，使得本地数据线对和全局数据线对在一起被彼此连接的同时被预充电。 在命令执行状态下，命令执行不需要的数据线选择开关21,22之一处于打开状态。 类似地，可以提供仅包括对应于本地数据线对的预充电电路的半导体存储器件。

公开(公告)号：US20050201193A1

公开(公告)日：2005-09-15

申请号：US11074897

申请日：2005-03-09

申请人： Naoki Kuroda ,  Yuji Nakai

发明人： Naoki Kuroda ,  Yuji Nakai

IPC分类号： G06F12/00 ,  G06F12/04 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063

CPC分类号： G11C7/10 ,  G11C7/1006 ,  G11C2207/107

摘要： A plurality of logic circuits both access the DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

摘要翻译： 多个逻辑电路都通过访问电路访问DRAM块。 DRAM块的操作时钟设置在比逻辑电路的系统时钟更高的频率上。 来自逻辑电路的第一位宽的输出经过串行/并行转换为第二位宽的数据，并将数据写入DRAM块。

公开(公告)号：US20050201142A1

公开(公告)日：2005-09-15

申请号：US11072298

申请日：2005-03-07

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： G11C11/407 ,  G11C11/24

CPC分类号： G11C5/147 ,  G11C11/4074

摘要： A large capacity DRAM block, which is accessible by a logic circuit, includes a VBB/VPP power supply circuit. The other DRAM blocks accessible by a logic circuit share the VBB/VPP power supply circuit of the large capacity DRAM block as their VBB/VPP power supply circuit.

摘要翻译： 可由逻辑电路访问的大容量DRAM块包括VBB / VPP电源电路。 由逻辑电路可访问的其他DRAM块可将大容量DRAM块的VBB / VPP电源电路作为其VBB / VPP电源电路共享。

公开(公告)号：US06788565B2

公开(公告)日：2004-09-07

申请号：US10394262

申请日：2003-03-24

申请人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

发明人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

IPC分类号： G11C1140

CPC分类号： G11C11/405 ,  H01L27/108

摘要： A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有第一晶体管，第二晶体管具有连接到第一晶体管的源极或漏极的一部分的源极或漏极;以及第三晶体管，源极或漏极连接到第一晶体管， 第一晶体管的源极或漏极的另一部分。 第一晶体管在其通道中累积从第二和第三晶体管传送的电荷。

公开(公告)号：US6137713A

公开(公告)日：2000-10-24

申请号：US420576

申请日：1999-10-19

申请人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

发明人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/24 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C11/24 ,  G11C11/405 ,  G11C5/02 ,  G11C5/063 ,  H01L27/10885

摘要： Over an active region with two bent portions on a semiconductor substrate, first and second word lines extend to cross these bent portions and to be vertically spaced apart from each other. Around at the center of the active region, a capacitor for storing data thereon and a capacitor contact are formed. A first bit line contact, which is connected to the active region, is formed on the opposite side to the capacitor contact across the first word line over the active region. A second bit line contact, which is also connected to the active region, is formed on the opposite side to the capacitor contact across the second word line over the active region. These first and second bit line contacts are provided substantially symmetrically about the center of the memory cell. In a pair of memory cells adjacent to each other along bit lines, one vertical end of the active region in one of the memory cells is continuous with an associated vertical end of the active region in the other memory cell. And each of the first and second bit line contacts is shared between an adjacent pair of memory cells.

摘要翻译： 在半导体衬底上具有两个弯曲部分的有源区域上，第一和第二字线延伸以跨越这些弯曲部分并且彼此垂直间隔开。 在有源区域的中心附近形成用于存储数据的电容器和电容器触点。 连接到有源区域的第一位线触点形成在跨过有源区域的跨第一字线的电容器触点的相反侧。 还连接到有源区的第二位线触点形成在跨过有源区的跨越第二字线的电容器触点的相反侧。 这些第一和第二位线触点基本上围绕存储器单元的中心对称地设置。 在沿着位线彼此相邻的一对存储单元中，一个存储单元中的有源区的一个垂直端与另一个存储单元中的有源区的相关联的垂直端连续。 并且第一和第二位线触点中的每一个在相邻的一对存储单元之间共享。

公开(公告)号：US20100178879A1

公开(公告)日：2010-07-15

申请号：US12730310

申请日：2010-03-24

申请人： Yusuke Sato ,  Nobuyoshi Maejima ,  Tomoaki Kudaishi ,  Shinji Moriyama ,  Naoki Kuroda ,  Ryota Sato ,  Masashi Okano

发明人： Yusuke Sato ,  Nobuyoshi Maejima ,  Tomoaki Kudaishi ,  Shinji Moriyama ,  Naoki Kuroda ,  Ryota Sato ,  Masashi Okano

IPC分类号： H04B1/04

CPC分类号： H03F3/195 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/451 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.

摘要翻译： 提供了一种技术，用于在增强电子设备的性能的同时，实现具有功率放大器电路的电子设备的尺寸的减小。 用于移动通信设备的RF功率模块包括安装在布线板上的第一和第二半导体芯片，无源部件以及第一和第二集成无源部件。 在第一半导体芯片中，形成用于GSM 900和DCS 1800的功率放大器电路的MISFET元件，并且还形成控制电路。 在第一集成无源部件中，形成用于GSM 900的低通滤波器电路，并且在第二集成无源部件中形成用于DCS 1800的低通滤波器电路。 在第二半导体芯片中，形成用于GSM 900和DCS 1800的天线切换电路。 在布线板的上表面上，第二半导体芯片设置在集成的无源元件之间的第一半导体芯片的旁边。

公开(公告)号：US07656732B2

公开(公告)日：2010-02-02

申请号：US12191011

申请日：2008-08-13

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： G11C7/02

CPC分类号： G11C11/4099 ,  G11C7/08 ,  G11C7/14 ,  G11C7/227

摘要： In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic circuit connected to a dummy data line of a dummy memory array are provided. A sense amplifier is activated in accordance with an output signal of the logic circuit.

摘要翻译： 在其中动态数据在位线上被放大和读取的诸如动态随机存取存储器（DRAM）的半导体存储装置中，连接到存储器阵列的数据线的数据线读出放大器/写入缓冲器和数据 提供连接到虚拟存储器阵列的虚拟数据线的线读出放大器控制信号产生逻辑电路。 读出放大器根据逻辑电路的输出信号而被激活。