A voltage level conversion circuit 101 is provided with a level converter 101a for converting a VDD1 system input signal into a VDD2 system signal, and a NOT circuit 30 for inverting the level-converted input signal and outputting the inverted signal, and the outputs of VDD1 system NOT circuits 21a and 21b constituting the level converter 101a are input to only high breakdown voltage transistors Qhn1 and Qhn2 in the level converter 101a while a signal having a logical voltage level corresponding to the low power supply voltage VDD2 is input to low breakdown voltage transistors Qlp1 and Qlp2, and further, only the input signal level-converted by the level converter 101a is input to the NOT circuit 30.