A system and method that process data in a circuitry utilizing two clocks. The two clocks may be an offset version of one another. Utilizing two clocks to processes the data may consume fewer clock cycles than using only one clock. The circuitry may comprise registers and a memory, wherein one register may receive a location of information in the memory, which may then be read from the received location. The one register may utilize a first of the two clocks, and the reading from the memory may utilize the second of the two clocks. The circuitry may comprise a portion of a CABAC decoder.