公开(公告)号：US07864839B2

公开(公告)日：2011-01-04

申请号：US11096467

申请日：2005-04-01

Applicant: Bo Zhang ,  Reinhard Schumann

Inventor： Bo Zhang ,  Reinhard Schumann

IPC: H04N7/12

CPC classification number: H04N19/53 ,  H04N19/102 ,  H04N19/103 ,  H04N19/124 ,  H04N19/146 ,  H04N19/172 ,  H04N19/176 ,  H04N19/177 ,  H04N19/56 ,  H04N19/91

Abstract: Described herein is a rate controller in a video system. The rate controller estimates a bit count, and controls three adaptive rate control loops. The master rate control loop is in control of the quantizer. The slave rate control loops control coarse motion estimation and fine motion estimation.

Abstract translation: 这里描述的是视频系统中的速率控制器。 速率控制器估计位计数，并控制三个自适应速率控制回路。 主速率控制回路控制量化器。 从速率控制循环控制粗略运动估计和精细运动估计。

公开(公告)号：US07800399B1

公开(公告)日：2010-09-21

申请号：US12462581

申请日：2009-08-04

Applicant: Reinhard Schumann

Inventor： Reinhard Schumann

IPC: H03K19/003

CPC classification number: H03K19/0005 ,  H04L25/0272 ,  H04L25/0298

Abstract: According to one exemplary embodiment, a termination circuit includes a number of drivers configured to receive source data on an input bus and to drive an output bus including a number of output lines. In the termination circuit the output lines are terminated by resistors, where one resistor is coupled between each output line and a common capacitor node. The termination circuit further includes a virtual regulator at the drivers, configured to control a termination voltage at the capacitor node by inputting compensation data into the drivers during idle cycles to achieve a net average 50% duty cycle. The virtual regulator can determine which cycles are idle by detecting an idle code in the source data.

Abstract translation: 根据一个示例性实施例，终端电路包括多个驱动器，其被配置为在输入总线上接收源数据并驱动包括多个输出线的输出总线。 在终端电路中，输出线由电阻器端接，其中一个电阻器耦合在每个输出线路和公共电容器节点之间。 终端电路还包括在驱动器处的虚拟调节器，其被配置为通过在空闲周期期间将补偿数据输入到驱动器中来控制电容器节点处的终端电压，以实现净平均50％占空比。 虚拟调节器可以通过检测源数据中的空闲代码来确定哪些周期是空闲的。

公开(公告)号：US07366823B2

公开(公告)日：2008-04-29

申请号：US11126501

申请日：2005-05-11

Applicant: Reinhard Schumann

Inventor： Reinhard Schumann

IPC: G06F12/00

CPC classification number: G06F12/0607

Abstract: Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data are read alternatively from each memory chip. The size of a block of data is determined by the bit width of a word and the number or memory arrays in a chip.

Abstract translation: 这里描述了用于存储器访问的方法和系统。 随着数字信号处理应用的复杂性增加，设计可能需要多个存储器芯片。 为了优化从存储器芯片访问的数据的带宽，数据块从每个存储器芯片交替地读取。 数据块的大小由字的位宽和芯片中的数量或存储器阵列决定。

公开(公告)号：US20050259747A1

公开(公告)日：2005-11-24

申请号：US10917914

申请日：2004-08-13

Applicant: Reinhard Schumann

Inventor： Reinhard Schumann

IPC: H04N7/12 ,  H04N7/26

CPC classification number: H04N19/42 ,  H04N19/16 ,  H04N19/176 ,  H04N19/44 ,  H04N19/91

Abstract: Described herein is a context adaptive binary arithmetic code decoder for decoding macroblock adaptive field/frame coded video data. In one embodiment, there is presented a video system. The video system comprises a CABAC decoder and neighbor buffer. The CABAC decoder decodes CABAC symbols associated with a portion of a picture, thereby resulting in decoded CABAC symbols. The neighbor buffer stores information from decoded CABAC symbols associated with another portion of the picture, said another portion being adjacent to the portion. The CABAC decoder decodes the CABAC symbols based on the information about the another portion of the picture.

Abstract translation: 这里描述了用于解码宏块自适应场/帧编码视频数据的上下文自适应二进制算术码解码器。 在一个实施例中，呈现了视频系统。 视频系统包括CABAC解码器和相邻缓冲器。 CABAC解码器解码与图像的一部分相关联的CABAC符号，从而导致解码的CABAC符号。 相邻缓冲器存储来自与图片的另一部分相关联的解码CABAC符号的信息，所述另一部分与该部分相邻。 CABAC解码器基于关于图片的另一部分的信息来解码CABAC符号。

公开(公告)号：US4045782A

公开(公告)日：1977-08-30

申请号：US671730

申请日：1976-03-29

Applicant: Terry M. Anderson ,  Reinhard Schumann

Inventor： Terry M. Anderson ,  Reinhard Schumann

IPC: G06F9/22 ,  G06F13/24 ,  G06F13/42 ,  G06F9/16 ,  G06F13/00

CPC classification number: G06F13/24 ,  G06F13/4243 ,  G06F9/226

Abstract: A data processing system including a central processing unit and external memory. The central processing unit has an arithmetic logic unit having first and second inputs and an output for outputting data. The arithmetic logic unit inputs are selectively connected to the outputs of a plurality of addressable registers which registers have inputs connectable to the arithmetic logic unit output for receiving and storing data therefrom. Additionally, the central processing unit has a read only memory capable of storing a plurality of addressable control instructions and having a plurality of outputs for supplying control signals in dependence upon the addressed control instructions and means capable of addressing control instructions stored in the read only memory in a predetermined sequence, or addressing a selected one of said word locations in dependence upon the data outputted from the arithmetic logic unit. The central processing unit, additionally, has a means for carrying signals adapted to be applied to the external memory for addressing the external memory and for storing data therein.

公开(公告)号：US20060222063A1

公开(公告)日：2006-10-05

申请号：US11096467

申请日：2005-04-01

Applicant: Bo Zhang ,  Reinhard Schumann

Inventor： Bo Zhang ,  Reinhard Schumann

IPC: H04N11/04 ,  H04N7/12 ,  H04B1/66 ,  H04N11/02

CPC classification number: H04N19/53 ,  H04N19/102 ,  H04N19/103 ,  H04N19/124 ,  H04N19/146 ,  H04N19/172 ,  H04N19/176 ,  H04N19/177 ,  H04N19/56 ,  H04N19/91

Abstract: Described herein is a rate controller in a video system. The rate controller estimates a bit count, and controls three adaptive rate control loops. The master rate control loop is in control of the quantizer. The slave rate control loops control coarse motion estimation and fine motion estimation.

Abstract translation: 这里描述的是视频系统中的速率控制器。 速率控制器估计位计数，并控制三个自适应速率控制回路。 主速率控制回路控制量化器。 从速率控制循环控制粗略运动估计和精细运动估计。

公开(公告)号：US20050262459A1

公开(公告)日：2005-11-24

申请号：US10920501

申请日：2004-08-18

Applicant: Reinhard Schumann

Inventor： Reinhard Schumann

IPC: G01R31/317 ,  G06F17/50 ,  H03K5/00 ,  H03K5/13

CPC classification number: H03K5/133 ,  G01R31/31727 ,  H03K2005/00097

Abstract: A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various aspects of the invention may comprise experimentally determining delay characteristics of an on-chip variable delay circuit utilizing an on-chip test module. A delay control signal for an on-chip variable delay circuit may be determined based at least in part on the experimentally determined delay characteristics. Timing of a signal may be adjusted by inputting the signal and the delay control signal into the on-chip variable delay circuit. The time-adjusted signal may then be utilized in signal processing. Such signal processing may, for example, comprise receiving an input data timing signal, generating a delayed input data timing signal, and generating an output data timing signal based on the input data timing signal and the delayed input data timing signal.

Abstract translation: 一种用于利用确定的可变延迟元件的延迟并利用这种调谐信号来自动调整信号定时（例如，数据定时信号）的系统和方法。 本发明的各个方面可以包括利用片上测试模块实验地确定片上可变延迟电路的延迟特性。 可以至少部分地基于实验确定的延迟特性来确定用于片上可变延迟电路的延迟控制信号。 可以通过将信号和延迟控制信号输入到片上可变延迟电路来调整信号的定时。 时间调整后的信号随后可用于信号处理。 这种信号处理可以例如包括接收输入数据定时信号，产生延迟的输入数据定时信号，以及基于输入数据定时信号和延迟的输入数据定时信号产生输出数据定时信号。

公开(公告)号：US20050262375A1

公开(公告)日：2005-11-24

申请号：US10981218

申请日：2004-11-04

Applicant: Reinhard Schumann

Inventor： Reinhard Schumann

IPC: G06F1/08

CPC classification number: G06F13/4243

Abstract: A system and method that process data in a circuitry utilizing two clocks. The two clocks may be an offset version of one another. Utilizing two clocks to processes the data may consume fewer clock cycles than using only one clock. The circuitry may comprise registers and a memory, wherein one register may receive a location of information in the memory, which may then be read from the received location. The one register may utilize a first of the two clocks, and the reading from the memory may utilize the second of the two clocks. The circuitry may comprise a portion of a CABAC decoder.

Abstract translation: 使用两个时钟处理电路中的数据的系统和方法。 两个时钟可以是彼此的偏移版本。 利用两个时钟处理数据可能比仅使用一个时钟消耗更少的时钟周期。 电路可以包括寄存器和存储器，其中一个寄存器可以在存储器中接收信息的位置，然后可以从接收到的位置读取信息的位置。 一个寄存器可以利用两个时钟中的第一个，并且来自存储器的读取可以利用两个时钟中的第二个。 电路可以包括CABAC解码器的一部分。

公开(公告)号：US4894605A

公开(公告)日：1990-01-16

申请号：US159757

申请日：1988-02-24

Applicant: Diethelm Ringleb ,  Reinhard Schumann ,  Elsworth Stearns ,  Tom Stylianos, Jr. ,  John Sweeney

Inventor： Diethelm Ringleb ,  Reinhard Schumann ,  Elsworth Stearns ,  Tom Stylianos, Jr. ,  John Sweeney

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31715 ,  G01R31/2884 ,  G01R31/318505

Abstract: A method of performing continuity testing of individual lead sets bonded to an integrated semiconductor component with a continuity test circuit fabricated on the component. The continuity test circuit includes a plurality of current gates, each of which is associated with a different semiconductor component contact pad a lead set is bonded to. Each current gate includes a first terminal connected to the associated contact pad and a second terminal connected to a common conductor all the current gate second terminals are connected to. The common conductor terminates at a semiconductor component contact test pad a lead set is bonded to. Whenever a test signal is applied to either the first or second terminal of a current gate, a measurable response signal is generated by the current gate over the other terminal. Continuity testing of the lead sets bonded to the chip is performed by applying a test signal to either a wiring board conductor connected to the lead set being tested or a wiring board conductor connected to the lead set connected to the semicondcutor component test contact pad. A test probe is then applied to the board conductor the test signal is not applied to. If the response signal is sensed, the leads are properly bonded; if no response signal is detected either the lead set being tested on the lead set connected to the semiconductor component is improperly bonded. The current gate blocks signals on the first terminal from appearing on the second terminal or the common conductor. Thus, when the semiconductor component is in use, the continuity test circuit is isolated from the other individual circuit components forming the integrated semiconductor component.

Abstract translation: 通过在该部件上制造的连续性测试电路，对与集成半导体部件结合的各个引线组进行连续性测试的方法。 连续性测试电路包括多个电流门，每个电流门与不同的半导体元件接触焊盘相关联，引线组接合到其上。 每个电流门包括连接到相关联的接触焊盘的第一端子和连接到公共导体的第二端子，所有当前栅极第二端子都连接到其上。 公共导体终止于半导体元件接触测试焊盘，引线组被连接到。 无论何时一个测试信号被施加到当前门的第一或第二端，在另一个终端上由当前门产生可测量的响应信号。 通过将测试信号施加到连接到被测试引线组的布线板导体或连接到连接到半切割器部件测试接触垫的引线组的布线板导体，进行与芯片接合的引线组的连续性测试。 然后将测试探头施加到板导体上，不应用测试信号。 如果检测到响应信号，则引线被适当地接合; 如果没有检测到响应信号，则在连接到半导体部件的引线组上测试的引线组不正确地接合。 当前门阻止第一端子上的信号出现在第二端子或公共导体上。 因此，当使用半导体部件时，连续性测试电路与形成集成半导体部件的其它各个电路部件隔离。

公开(公告)号：US3969724A

公开(公告)日：1976-07-13

申请号：US565239

申请日：1975-04-04

Applicant: Terry M. Anderson ,  Reinhard Schumann

Inventor： Terry M. Anderson ,  Reinhard Schumann

IPC: G06F9/26 ,  G06F9/40 ,  G06F9/14 ,  G06F9/18

CPC classification number: G06F9/4425 ,  G06F9/265

Abstract: A central processing unit (CPU) is disclosed which can be used in a microprocessor and which has a relatively simple architecture enabling it to perform rapid data processing operations. The CPU has a plurality of registers, an arithmetic logic unit (ALU), and a multiplexor which selects one of the ALU operands. A relatively large scratchpad is included in the CPU to eliminate time-consuming addressing of memories outside the CPU. A parallel architecture and the ability to perform simultaneous operations also enhance the CPU speed. The CPU control unit has a read only memory (ROM) for storage of micro control instructions and a program counter capable of addressing the ROM either sequentially or in accordance with a specific address for execution of jump instructions.

Abstract translation: 公开了一种中央处理单元（CPU），其可以在微处理器中使用，并且具有相对简单的架构，使得其能够执行快速的数据处理操作。 CPU具有多个寄存器，算术逻辑单元（ALU）和选择ALU操作数之一的复用器。 CPU中包含相对较大的暂存器，以消除CPU外部的存储器的耗时寻址。 并行架构和执行同时操作的能力也提高了CPU速度。 CPU控制单元具有用于存储微控制指令的只读存储器（ROM）和能够顺序地或根据用于执行跳转指令的特定地址寻址ROM的程序计数器。