发明申请
- 专利标题: Via etch process
- 专利标题(中): 通过蚀刻工艺
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申请号: US10854541申请日: 2004-05-25
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公开(公告)号: US20050274690A1公开(公告)日: 2005-12-15
- 发明人: Hyun-Mog Park , Vijayakumar Ramachandrarao
- 申请人: Hyun-Mog Park , Vijayakumar Ramachandrarao
- 主分类号: B44C1/22
- IPC分类号: B44C1/22 ; H01L21/306 ; H01L21/311 ; H01L21/768
摘要:
Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.
公开/授权文献
- US07303648B2 Via etch process 公开/授权日:2007-12-04