发明申请
- 专利标题: CHIP SCALE PACKAGE WITH OPEN SUBSTRATE
- 专利标题(中): 具有开放基板的芯片尺寸包装
-
申请号: US10866561申请日: 2004-06-10
-
公开(公告)号: US20050277227A1公开(公告)日: 2005-12-15
- 发明人: Il Shim , Kwee Tan , Jian Li , Dario Filoteo
- 申请人: Il Shim , Kwee Tan , Jian Li , Dario Filoteo
- 申请人地址: SG Singapore
- 专利权人: ST ASSEMBLY TEST SERVICES LTD.
- 当前专利权人: ST ASSEMBLY TEST SERVICES LTD.
- 当前专利权人地址: SG Singapore
- 主分类号: H01L21/44
- IPC分类号: H01L21/44 ; H01L21/48 ; H01L23/13 ; H01L23/498 ; H01L25/065 ; H01L25/10
摘要:
A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
公开/授权文献
- US07008820B2 Chip scale package with open substrate 公开/授权日:2006-03-07
信息查询
IPC分类: