发明申请
- 专利标题： Method and system for modeling variation of circuit parameters in delay calculation for timing analysis
- 专利标题（中）： 用于时序分析的延迟计算中电路参数变化的方法和系统
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申请号： US11014096申请日： 2004-12-15
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公开(公告)号： US20050278671A1公开(公告)日： 2005-12-15
- 发明人: Nishath Verghese , Hong Zhao
- 申请人： Nishath Verghese , Hong Zhao
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in the circuit parameter range. An interpolation process generates an equation to calculate delay using the characterization data from the three circuit parameter values. This delay equation calculates the delay for any value in the circuit parameter range. Similar methodology is used to model simultaneous variation of two circuit parameters. The cell is characterized at just six circuit parameter pairs to interpolate the delay equation for any circuit parameter pair in the characterized ranges. This methodology can be extended to accommodate variation of multiple circuit parameters using similar interpolation techniques.
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