发明申请
- 专利标题： Semiconductor memory device and circuit layout of dummy cell
- 专利标题（中）： 半导体存储器件和虚拟电池的电路布局
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申请号： US11156706申请日： 2005-06-21
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公开(公告)号： US20050286323A1公开(公告)日： 2005-12-29
- 发明人: Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
- 申请人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
- 申请人地址： JP Osaka
- 专利权人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人地址： JP Osaka
- 优先权： JP2004-185163 20040623
- 主分类号： G11C7/08
- IPC分类号： G11C7/08 ; G11C7/12 ; G11C11/413 ; G11C29/00
摘要：
A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.