Provided are a memory control apparatus and method for controlling an order of processing memory access commands from a plurality of master devices when the master devices access a memory to improve a processing speed. The memory controller includes a command queue receiving memory access commands from at least one master device and storing the memory access commands; a determination unit analyzing addresses of a memory, which will be accessed by the received commands, to control an order of processing the stored commands; and a command interpreter interpreting a command output under the control of the determination unit to output an address related signal. Accordingly, a command processing speed is remarkably improved without increasing a system size.