发明申请
US20050289330A1 Branch control method and information processor 审中-公开
分支控制方法和信息处理器

Branch control method and information processor
摘要:
An object of the present invention is to provide a branch control method and an information processor in which when an instruction that can be processed in a delayed slot is present, a delayed branch is implemented to eliminate a branch hazard, and even when there is no such an instruction that can be processed in the delayed slot, the program is not increased in size because insertion of NOP into instruction memory is not necessary. To achieve this object, in an information processor which performs pipeline processing of instructions, branch operation is controlled as follows. When a conditional branch instruction is executed, whether or not to implement a delayed branch is determined according to whether or not the branch condition is satisfied and the value of a given control filed contained in an instruction code located at an address successive to the conditional branch instruction. When it is determined that no delayed branch is implemented and the branch condition is satisfied, the successive instruction is fetched but is not executed, while an instruction at a branch destination is fetched and executed. When it is determined that no delayed branch is implemented and the branch condition is not satisfied, the instruction successive to the branch instruction is executed.
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