公开(公告)号：US07614572B2

公开(公告)日：2009-11-10

申请号：US10588729

申请日：2004-11-26

申请人： Naoki Yamaguchi ,  Shunichi Nagasawa ,  David Edward Wilson ,  Masayuki Yamasaki

发明人： Naoki Yamaguchi ,  Shunichi Nagasawa ,  David Edward Wilson ,  Masayuki Yamasaki

IPC分类号： B05B5/00 ,  B05B1/00 ,  B05B9/04 ,  B65D1/32 ,  A01G25/14

CPC分类号： B05B5/1691 ,  B05B9/0866

摘要： An electrostatic spraying device has a removable cartridge with a reservoir containing a volume of liquid compositions to be electrically sprayed. The reservoir is deformable according to inner pressure and configured to provide a removable cartridge. The device includes a dispensing unit for spraying the liquid composition. The dispensing unit includes a nozzle for dispensing the liquid composition and an emitter electrode which charges the liquid composition for electrostatically spraying the liquid composition out through the nozzle. A suction pump is integrated into the dispensing unit in an immediately upstream relation with the reservoir for feeding the liquid composition from the reservoir to the nozzle. Thus, the suction pump can be concentrated together with the emitter electrode and the nozzle into the dispensing unit on one end of the reservoir, enabling to realize the cartridge of a compact design.

摘要翻译： 一种静电喷涂装置具有一个带有一个储存器的可移除的盒，该容器包含一定量的待电喷雾的液体组合物。 储存器可根据内部压力变形并且被配置成提供可移除的盒。 该装置包括用于喷射液体组合物的分配单元。 分配单元包括用于分配液体组合物的喷嘴和向液体组合物充电的发射电极，用于通过喷嘴静电喷射液体组合物。 抽吸泵以与储存器紧密上游的关系集成到分配单元中，用于将液体组合物从储存器供给到喷嘴。 因此，抽吸泵可以与发射电极和喷嘴一起集中在储存器一端的分配单元中，使得能够实现紧凑设计的盒。

公开(公告)号：US06785799B1

公开(公告)日：2004-08-31

申请号：US09514204

申请日：2000-02-25

申请人： Masayuki Yamasaki ,  Katsuhiko Ueda

发明人： Masayuki Yamasaki ,  Katsuhiko Ueda

IPC分类号： G06F1500

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3867 ,  G06F9/3885 ,  G06F15/8007 ,  G06F15/8053

摘要： A multiprocessor includes M banks storing a plurality of instructions; and N processors each having N instruction fetch stages, wherein each of the N processors processes one of the plurality of instructions in a pipelined manner, where N is an integer equal to or greater than 2, and M is an integer equal to or greater than N, wherein each of the N processors fetches one of the plurality of instructions at a different instruction fetch stage from instruction fetch stages used by other processors.

摘要翻译： 多处理器包括存储多个指令的M个存储体; 和N个处理器，每个N个处理器具有N个指令获取阶段，其中N个处理器中的每个处理器以流水线方式处理多个指令之一，其中N是等于或大于2的整数，M是等于或大于 N，其中N个处理器中的每个处理器在由其他处理器使用的指令提取阶段的不同指令提取阶段处获取多个指令中的一个。

公开(公告)号：US06754870B2

公开(公告)日：2004-06-22

申请号：US09833787

申请日：2001-04-13

申请人： Takao Yoshida ,  Minoru Okamoto ,  Masayuki Yamasaki ,  Kazuhiro Okabayashi

发明人： Takao Yoshida ,  Minoru Okamoto ,  Masayuki Yamasaki ,  Kazuhiro Okabayashi

IPC分类号： H03M1300

CPC分类号： H03M13/091 ,  G06F9/3879 ,  H03M13/6516 ,  H03M13/6569

摘要： To enable high-speed CRC operation and flexible use of various generating polynomials without causing significant increase in circuit scale, the CRC operation unit uses circuits generally provided for a DSP and some additional circuits. The CRC operation unit includes: a generating polynomial supply section having a first general register for storing an arbitrary generating polynomial and a selector for selectively outputting the generating polynomial or data of which all bits has a value of 0; an operation data supply section having a memory, a shift register, a second general register, and a barrel shifter, for outputting operation data for CRC operation based on transmitting/receiving data; an operation section for performing CRC operation using the generating polynomial output from the generating polynomial supply section and the operation data output from the operation data supply section; and an operation instruction execution control section for controlling the operations of the above sections.

摘要翻译： 为了实现高速CRC操作和灵活使用各种生成多项式而不引起电路规模的显着增加，CRC操作单元使用通常为DSP提供的电路和一些附加电路。 CRC操作单元包括：生成多项式提供部分，具有用于存储任意生成多项式的第一通用寄存器和用于选择性地输出所有位具有值0的生成多项式或数据的选择器; 具有存储器，移位寄存器，第二通用寄存器和桶形移位器的操作数据提供部分，用于基于发送/接收数据输出用于CRC操作的操作数据; 操作部分，用于使用从生成多项式提供部分输出的生成多项式和从操作数据提供部分输出的操作数据来执行CRC操作; 以及操作指令执行控制部分，用于控制上述部分的操作。

公开(公告)号：US06370638B1

公开(公告)日：2002-04-09

申请号：US09195529

申请日：1998-11-18

申请人： Masayuki Yamasaki

发明人： Masayuki Yamasaki

IPC分类号： G06F900

CPC分类号： G06F9/30079 ,  G06F9/3836 ,  G06F9/3867

摘要： A program control apparatus for processing an instruction by using a pipeline processing for providing the effective stall control when resource competition is caused by the instructions is disclosed. The NOP field which shows the number of NOP (no operation processing) instruction is assigned in the instruction code with the possibility to cause the resource competition, and set the number of NOP for the stall and performs the NOP according to the NOP field. When the NOP field of the following instruction shows N, stall is executed by inserting and performing NOP of N piece by the stall control part 3 before the following instruction is executed. When the NOP field is assigned in both a preceding instruction and a following instruction, NOP of predetermined number N piece is inserted after the preceding instruction is executed, NOP of predetermined number M piece is inserted before the following instruction is executed, and the stall is achieved.

摘要翻译： 公开了一种程序控制装置，用于通过使用用于在由指令引起资源竞争时提供有效失速控制的流水线处理来处理指令。 在指令代码中分配了NOP（无操作处理）指令的NOP字段，其中可能导致资源竞争，并且设置停止的NOP数量并根据NOP字段执行NOP。 当以下指令的NOP字段显示N时，在执行以下指令之前，由失速控制部分3插入并执行N段的NOP来执行失速。 当在先前指令和后续指令中分配NOP字段时，在执行前一条指令之后插入预定数量N的NOP，在执行后续指令之前插入预定数量M的NOP，并且失速是 实现了

公开(公告)号：US20110010529A1

公开(公告)日：2011-01-13

申请号：US12885891

申请日：2010-09-20

申请人： Masayuki Yamasaki

发明人： Masayuki Yamasaki

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3004 ,  G06F9/30087

摘要： With conventional ordered data reference instructions, an instruction which is to be the subject of an execution order guarantee cannot be separately specified, and a resource which is to be the subject of an execution order guarantee likewise cannot be specified and thus instruction movement is restricted more than necessary in the out-of-order execution of instructions and so on and performance deterioration becomes significant particularly in the case of performing data transfer to a resource having high access latency. Consequently, the field of an ordered data reference instruction judged to include a predetermined field is decoded so as to identify a subject instruction which is specified by the ordered data reference instruction and is the subject of execution order guarantee, and guarantee the execution order of the subject instruction with respect to the execution of the identified ordered data reference instruction.

摘要翻译： 对于传统的有序数据参考指令，不能单独指定作为执行顺序保证的对象的指令，并且不能指定作为执行顺序保证对象的对象的资源，因此指令移动被限制更多 比指令等的无序执行所必需，并且性能劣化特别是在对具有高访问等待时间的资源进行数据传送的情况下变得显着。 因此，被判定为包括预定字段的有序数据参考指令的字段被解码，以便识别由有序数据参考指令指定的主题指令，并且是执行命令保证的对象，并且保证执行顺序 关于执行所识别的有序数据参考指令的主题指令。

公开(公告)号：US06751773B2

公开(公告)日：2004-06-15

申请号：US09833061

申请日：2001-04-12

申请人： Kazuhiro Okabayashi ,  Minoru Okamoto ,  Masayuki Yamasaki

发明人： Kazuhiro Okabayashi ,  Minoru Okamoto ,  Masayuki Yamasaki

IPC分类号： H03M1303

CPC分类号： H03M13/23

摘要： A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.

摘要翻译： 编码装置包括移位寄存器，输入寄存器和逻辑运算部。 移位寄存器在输入位序列上执行位移位，并将输入位序列的一位相继存储。 输入寄存器存储关于生成多项式的各个阶的项的系数。 逻辑运算部分获得存储在移位寄存器上的相应位的逻辑积和存储在输入寄存器上的相关位以及输入到移位寄存器的每一位的逻辑积和存储在输入寄存器上的关联位， 输入一位输入比特序列，输入比特关联的多项式项中的系数中的高阶一个。 接下来，逻辑运算部分导出乘积的异或逻辑和，然后输出和作为代码序列的位。

公开(公告)号：US20050289330A1

公开(公告)日：2005-12-29

申请号：US11157920

申请日：2005-06-22

申请人： Masayuki Yamasaki

发明人： Masayuki Yamasaki

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3804

摘要： An object of the present invention is to provide a branch control method and an information processor in which when an instruction that can be processed in a delayed slot is present, a delayed branch is implemented to eliminate a branch hazard, and even when there is no such an instruction that can be processed in the delayed slot, the program is not increased in size because insertion of NOP into instruction memory is not necessary. To achieve this object, in an information processor which performs pipeline processing of instructions, branch operation is controlled as follows. When a conditional branch instruction is executed, whether or not to implement a delayed branch is determined according to whether or not the branch condition is satisfied and the value of a given control filed contained in an instruction code located at an address successive to the conditional branch instruction. When it is determined that no delayed branch is implemented and the branch condition is satisfied, the successive instruction is fetched but is not executed, while an instruction at a branch destination is fetched and executed. When it is determined that no delayed branch is implemented and the branch condition is not satisfied, the instruction successive to the branch instruction is executed.

摘要翻译： 本发明的目的是提供一种分支控制方法和信息处理器，其中当存在可以在延迟时隙中处理的指令时，实施延迟分支以消除分支危险，并且即使当没有 可以在延迟时隙中处理这样的指令，程序没有增大，因为不需要将NOP插入到指令存储器中。 为了实现该目的，在执行指令的流水线处理的信息处理器中，如下控制分支操作。 当执行条件转移指令时，根据分支条件是否被满足以及包含在位于与条件分支连续的地址的指令代码中的给定控制字段的值来确定是否实现延迟分支 指令。 当确定没有实现延迟分支并且分支条件被满足时，获取并执行在分支目的地的指令时，连续指令被取出但不被执行。 当确定没有实现延迟分支并且不满足分支条件时，执行与分支指令相连的指令。

公开(公告)号：US06182211B2

公开(公告)日：2001-01-30

申请号：US09106083

申请日：1998-06-29

申请人： Masayuki Yamasaki

发明人： Masayuki Yamasaki

IPC分类号： G06F942

CPC分类号： G06F9/30058 ,  G06F9/3842

摘要： In order to effectively reduce branch hazards without a restriction to a structure of a pipeline, the contents of instructions and the like during control of conditional branching in an information processing apparatus which processes an instruction by pipeline processing, before a condition of a conditional branch instruction becomes defined, that is, before a branch judgement is made, pipeline information of a subsequent instruction which is subsequent to the conditional branch instruction is saved so that an instruction beyond a branch is fed to a pipeline in advance. When the condition is met, the instruction beyond the branch is executed as it directly is. When the condition is not met, the saved pipeline information of the subsequent instruction is returned to the pipeline and the subsequent instruction which is subsequent to the conditional branch instruction is executed.

摘要翻译： 为了有效地减少分支危害而不限制流水线的结构，在条件分支控制期间的指令等的内容在处理通过流水线处理的指令的信息处理装置中，在条件分支指令的条件之前 即，在进行分支判断之前，保存在条件分支指令之后的后续指令的流水线信息，使得超过分支的指令被预先馈送到流水线。 当条件满足时，分支之外的指令将直接执行。 当不满足条件时，将后续指令的保存的流水线信息返回到流水线，并执行在条件转移指令之后的后续指令。

公开(公告)号：US20080270658A1

公开(公告)日：2008-10-30

申请号：US12108754

申请日：2008-04-24

申请人： Keisuke KANEKO ,  Takao YAMAMOTO ,  Masayuki YAMASAKI ,  Nobuo HIGAKI ,  Kazushi KURATA ,  Ryuta NAKANISHI

发明人： Keisuke KANEKO ,  Takao YAMAMOTO ,  Masayuki YAMASAKI ,  Nobuo HIGAKI ,  Kazushi KURATA ,  Ryuta NAKANISHI

IPC分类号： G06F13/372

CPC分类号： G06F13/1663

摘要： Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU0 and PU1 each of which issues an access request for accessing the shared memory, a bus IF unit 4-10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request; and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4-10 restricts the number of consecutive transfer phase executions corresponding to the plural access requests to be not more than N.

摘要翻译： 提供了一种简单结构化的多处理器系统，其在访问共享存储器的多个主单元中均等地分配用于访问共享存储器的访问性能。 多处理器系统包括多个主单元PU 0和PU 1，每个主单元PU 0和PU 1发出访问共享存储器的访问请求;总线IF单元4-10，其通过拆分事务方案访问总线，并且单独执行用于接受共享存储器的请求阶段 访问请求; 以及用于响应于接受的访问请求执行数据传送的传送阶段。 在其中一个主单元连续发出多个接入请求而没有预定时间段的间隔的情况下，总线IF单元4-10将与多个接入请求相对应的连续传输相位执行的数量限制为不大于N 。

公开(公告)号：US06842852B1

公开(公告)日：2005-01-11

申请号：US09500086

申请日：2000-02-08

申请人： Masayuki Yamasaki ,  Minoru Okamoto

发明人： Masayuki Yamasaki ,  Minoru Okamoto

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/30061 ,  G06F9/30072

摘要： An execution control instruction is applied to an information processor of the type processing instructions by pipelining to suppress the occurrence of branch hazard. The execution control instruction contains: a condition field for specifying an execution condition; and an instruction-specifying field for defining, in binary code, the number of instructions to be executed only conditionally. In response to the execution control instruction, a nullification controller decides, based on control flags provided from an arithmetic logic unit, whether or not the execution condition specified by the condition field is satisfied. And based on the outcome of this decision, the controller determines whether or not that number of instructions, which has been defined by the instruction-specifying field for instructions succeeding the execution control instruction, should be nullified. If the controller has determined that the specified number of succeeding instructions should be nullified since the execution condition is not met, then the controller asserts a nullification signal to be supplied to the arithmetic logic unit. In this manner, a large number of succeeding instructions are executable conditionally using an execution control instruction of a short word length.

摘要翻译： 通过流水线将执行控制指令应用于类型处理指令的信息处理器，以抑制分支危险的发生。 执行控制指令包含：用于指定执行条件的条件字段; 以及指令指定字段，用于以二进制代码定义仅有条件地执行的指令的数量。 响应于执行控制指令，无效控制器基于从算术逻辑单元提供的控制标志来确定是否满足由条件字段指定的执行条件。 并且，根据该决定的结果，控制器判定是否将由执行控制指令之后的指令指定指定字段定义的指令数量无效。 如果由于执行条件不满足控制器已经确定指定数量的后续指令将被取消，则控制器断言要提供给算术逻辑单元的无效信号。 以这种方式，大量的后续指令可以使用短字长度的执行控制指令有条件地执行。