Invention Application
US20060002180A1 Random access memory array with parity bit structure 有权
具有奇偶校验位结构的随机存取存储器阵列

  • Patent Title: Random access memory array with parity bit structure
  • Patent Title (中): 具有奇偶校验位结构的随机存取存储器阵列
  • Application No.: US10880980
    Application Date: 2004-06-30
  • Publication No.: US20060002180A1
    Publication Date: 2006-01-05
  • Inventor: Christophe Frey
  • Applicant: Christophe Frey
  • Applicant Address: US TX Carrollton
  • Assignee: STMicroelectronics, Inc.
  • Current Assignee: STMicroelectronics, Inc.
  • Current Assignee Address: US TX Carrollton
  • Main IPC: G11C11/00
  • IPC: G11C11/00
Random access memory array with parity bit structure
Abstract:
A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells.
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