公开(公告)号：US20060002180A1

公开(公告)日：2006-01-05

申请号：US10880980

申请日：2004-06-30

Applicant: Christophe Frey

Inventor： Christophe Frey

IPC: G11C11/00

CPC classification number: G06F11/1076 ,  G11C7/1006 ,  G11C11/16 ,  G11C16/10 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells.

Abstract translation: 随机存取存储器阵列包括以多个行和列排列的用于在多个存储器位置存储数据字的第一随机存取存储器元件。 存储器阵列还包括布置在至少一个附加列中的第二随机存取存储器元件。 每个第二随机存取存储器元件与存储器位置相关联，以存储指示存储在该存储器位置的数据字是真还是补补版本的标志值。 各个存储元件可以包括磁性随机存取存储器元件。 或者，各个存储元件可以包括闪存单元。

公开(公告)号：US06590812B2

公开(公告)日：2003-07-08

申请号：US10178081

申请日：2002-06-21

Applicant: Christophe Frey

Inventor： Christophe Frey

IPC: G11C710

CPC classification number: G11C11/41

Abstract: A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between the first node linked to the bit line and a third node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.

Abstract translation: 存储单元形成有缓冲电路。 缓冲电路的输出端与输入端相连，构成逻辑锁存器。 写访问晶体管设置在链接到位线的第一节点和缓冲电路的输入之间。 写存取晶体管的控制栅极链接到链接到写字线的第二节点，并且读访问晶体管设置在链接到位线的第一节点和链接到读字线的第三节点之间。 读取存取晶体管的控制栅极连接到缓冲电路的输出端。

公开(公告)号：US06424580B1

公开(公告)日：2002-07-23

申请号：US09556044

申请日：2000-04-21

Applicant: Christophe Frey

Inventor： Christophe Frey

IPC: G11C700

CPC classification number: G11C11/419 ,  G11C7/12

Abstract: An integrated circuit includes an array of memory cells that are selected by rows and read by columns. The columns are first precharged by an internal signal to then read the memory cells. The read is responsive to an edge of a clock signal and the read is of an unknown delay. A multiplexer output provides the internal signal. The multiplexer includes a plurality of inputs electrically connected to delay lines of different delay sizes that receive the edge of the clock signal. A multiplexer control circuit selects a delay line to provide the internal signal as soon as possible after the unknown delay.

Abstract translation: 集成电路包括由行选择并由列读取的存储器单元阵列。 这些列首先由内部信号预先充电，然后读取存储单元。 读取响应于时钟信号的边沿，并且读取是未知的延迟。 多路复用器输出提供内部信号。 多路复用器包括电连接到接收时钟信号边缘的不同延迟大小的延迟线的多个输入。 多路复用器控制电路在未知延迟之后尽可能快地选择延迟线来提供内部信号。

公开(公告)号：US07301800B2

公开(公告)日：2007-11-27

申请号：US10881746

申请日：2004-06-30

Applicant: Christophe Frey

Inventor： Christophe Frey

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C11/5607

Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines, the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store information within the element in any one of at least three logic states.

Abstract translation: 磁性随机存取存储元件由第一磁性隧道结和第二磁性隧道结形成。 这些磁性隧道结在串联电阻电路中相互连接。 连接的第一和第二磁性隧道结通过存取晶体管连接到位线。 写入位线和写入数据线与第一和第二磁性隧道结中的每一个相关联。 通过向这些线路施加适当的电流，可以控制与第一和第二磁性隧道结中的每一个的磁矢量取向，以便以至少三个逻辑状态中的任何一个存储元件内的信息。

公开(公告)号：US07139212B2

公开(公告)日：2006-11-21

申请号：US11152033

申请日：2005-06-14

Applicant: Cyrille Dray ,  Sébastien Barasinski ,  Jean Lasseuguette ,  Christophe Frey ,  Richard Fournel

Inventor： Cyrille Dray ,  Sébastien Barasinski ,  Jean Lasseuguette ,  Christophe Frey ,  Richard Fournel

IPC: G11C8/00

CPC classification number: G11C11/16

Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Abstract translation: 存储器件包括由至少一个写入段形成的至少一个分段写入线。 编程电路由存储器件的写入模式中的行地址电路控制，以对耦合到分段写入线的至少一个存储单元进行编程。 读取位线连接到用于在存储器件的读取模式下读取单元的内容的读取电路。 读取位线以写入模式与线路地址电路协作，以控制分段写入线的编程电路。

公开(公告)号：US20050281080A1

公开(公告)日：2005-12-22

申请号：US11159858

申请日：2005-06-23

Applicant: Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sebastien Barasinski ,  Richard Fournel

Inventor： Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sebastien Barasinski ,  Richard Fournel

IPC: G11C7/18 ,  G11C8/10 ,  G11C11/16 ,  G11C11/14

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。 第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且 相应的写位线将数据写入该列中的至少一个存储器元件。

公开(公告)号：US07696649B2

公开(公告)日：2010-04-13

申请号：US11889456

申请日：2007-08-13

Applicant: Christophe Frey ,  Andrew John Sowden

Inventor： Christophe Frey ,  Andrew John Sowden

IPC: H01H7/00 ,  H01H9/54

CPC classification number: H03K19/0016 ,  H03K17/28 ,  H03K17/30 ,  Y10T307/461 ,  Y10T307/937 ,  Y10T307/951 ,  Y10T307/957

Abstract: The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal and responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level.

Abstract translation: 所述功率控制电路包括一系列功率开关电路，每个功率开关电路与所述电路部分中的一个相关联并且被提供有使能信号，并响应于其使能信号被设置为将所述电压源连接到所述至少一个电压 相关电路部分的线。 此外，提供至少一个使能限定电路，每个这样的使能限定电路与功率切换电路中的一个相关联，并且被布置成产生用于确定提供给该系列中的稍后电力开关电路的使能信号的输出信号。 当提供给相关联的功率开关电路的使能信号都被置位并且与该功率开关电路相关联的电路部分的至少一个电压线已经达到预定电压电平时，每个使能限定电路设置其输出信号。

公开(公告)号：US07209383B2

公开(公告)日：2007-04-24

申请号：US11159858

申请日：2005-06-23

Applicant: Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sébastien Barasinski ,  Richard Fournel

Inventor： Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sébastien Barasinski ,  Richard Fournel

IPC: G11C11/14

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。 第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且 相应的写位线将数据写入该列中的至少一个存储器元件。

公开(公告)号：US07079415B2

公开(公告)日：2006-07-18

申请号：US10881747

申请日：2004-06-30

Applicant: Christophe Frey

Inventor： Christophe Frey

IPC: G11C11/15

CPC classification number: G11C14/0081 ,  G11C11/16

Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.

Abstract translation: 磁性随机存取存储元件由第一磁性隧道结和第二磁性隧道结形成。 锁存电路包括连接到第一磁性隧道结的假节点和连接到第二磁性隧道结的真实节点。 与元件相关联地提供一对互补位线。 第一存取晶体管将位线中的假一个相互连接到锁存电路的假节点，而第二存取晶体管将位线中的真实位线连接到锁存电路的真实节点。 因此，存储元件具有SRAM四晶体管（4T）两负载（2R）架构，其中与两个磁隧道结相关联的电阻提供两个负载电阻。

公开(公告)号：US20060002191A1

公开(公告)日：2006-01-05

申请号：US11155012

申请日：2005-06-16

Applicant: Christophe Frey ,  David Turgis ,  Jean-Christophe Lafont

Inventor： Christophe Frey ,  David Turgis ,  Jean-Christophe Lafont

IPC: G11C11/34

CPC classification number: G11C11/412

Abstract: A memory cell (1), includes: a flip-flop (2) that has additional read/write terminals; a 1-bit write line (wb11); a first transistor (T4) switching between the 1-bit write line and the terminal, its gate being connected to a word selection line (W11); a 0-bit write line (wb10); a second transistor (T3) switching between the 0-bit write line and the terminal, its gate being connected to a word selection line (W12); a bit read line (b1r); and read transistors (T1, T2), with one of their gates being connected to a read/write terminal and the other being connected to a word selection line. The invention particularly allows the surface area and complexity of a memory cell to be reduced.

Abstract translation: 存储单元（1）包括：具有附加读/写端子的触发器（2）; 1位写入线（wb 11）; 第一晶体管（T 4）在1位写入线和端子之间切换，其栅极连接到字选择线（W 11）; 0位写行（wb 10）; 第二晶体管（T 3）在0位写入线和端子之间切换，其栅极连接到字选择线（W 12）; 读一行（b 1 r）; 并读取晶体管（T 1，T 2），其中一个栅极连接到读/写端子，另一个连接到字选择线。 本发明特别允许减小存储单元的表面积和复杂性。