Invention Application
US20060003511A1 Method of fabricating a semiconductor device with multiple gate oxide thicknesses
有权
制造具有多栅极氧化物厚度的半导体器件的方法
- Patent Title: Method of fabricating a semiconductor device with multiple gate oxide thicknesses
- Patent Title (中): 制造具有多栅极氧化物厚度的半导体器件的方法
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Application No.: US10880527Application Date: 2004-07-01
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Publication No.: US20060003511A1Publication Date: 2006-01-05
- Inventor: Francois Hebert , Salman Ahsan
- Applicant: Francois Hebert , Salman Ahsan
- Assignee: LINEAR TECHNOLOGY CORPORATION
- Current Assignee: LINEAR TECHNOLOGY CORPORATION
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/8234 ; H01L21/336

Abstract:
The individual performance of various transistors is optimized by tailoring the thickness of the gate oxide layer to a particular operating voltage. Embodiments include forming transistors with different gate oxide thicknesses by initially depositing one or more gate oxide layers with intermediate etching to remove the deposited oxide from active regions wherein transistors with relatively thinner gate oxides are to be formed, and then implementing one or more thermal oxidation steps. Embodiments include forming semiconductor devices comprising transistors with two different gate oxide thicknesses by initially depositing an oxide film, selectively removing the deposited oxide film from active areas in which low voltage transistors having a relatively thin gate oxide are to be formed, and then implementing thermal oxidation.
Public/Granted literature
- US07402480B2 Method of fabricating a semiconductor device with multiple gate oxide thicknesses Public/Granted day:2008-07-22
Information query
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