发明申请
US20060015708A1 Microprocessor with branch target determination in decoded microinstruction code sequence
审中-公开
微处理器在解码微指令代码序列中具有分支目标确定
- 专利标题： Microprocessor with branch target determination in decoded microinstruction code sequence
- 专利标题（中）： 微处理器在解码微指令代码序列中具有分支目标确定
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申请号： US10891166申请日： 2004-07-14
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公开(公告)号： US20060015708A1公开(公告)日： 2006-01-19
- 发明人: Darrell Boggs , Christopher Jones , Gary Brown
- 申请人： Darrell Boggs , Christopher Jones , Gary Brown
- 主分类号： G06F9/00
- IPC分类号： G06F9/00
摘要：
In a microprocessor, customer code routines are decoded from ISA instructions into microinstructions and stored in a customer code store (CCS) for later, repeated execution. Branch target addresses in the ISA code, which use an ISA memory addressing format, are replaced with CCS branch target addresses in the decoded, stored customer code routine. The customer code routine thus behaves as a microcoded library routine.
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