公开(公告)号：US20060015708A1

公开(公告)日：2006-01-19

申请号：US10891166

申请日：2004-07-14

申请人： Darrell Boggs ,  Christopher Jones ,  Gary Brown

发明人： Darrell Boggs ,  Christopher Jones ,  Gary Brown

IPC分类号： G06F9/00

CPC分类号： G06F9/3017 ,  G06F9/3808

摘要： In a microprocessor, customer code routines are decoded from ISA instructions into microinstructions and stored in a customer code store (CCS) for later, repeated execution. Branch target addresses in the ISA code, which use an ISA memory addressing format, are replaced with CCS branch target addresses in the decoded, stored customer code routine. The customer code routine thus behaves as a microcoded library routine.

摘要翻译： 在微处理器中，客户代码例程从ISA指令被解码为微指令，并存储在客户代码存储（CCS）中以供稍后重复执行。 使用ISA存储器寻址格式的ISA代码中的分支目标地址在解码的存储的客户代码例程中被CCS分支目标地址替换。 因此，客户代码例程作为微编码库例程。

公开(公告)号：US20060015707A1

公开(公告)日：2006-01-19

申请号：US10891165

申请日：2004-07-14

申请人： Gary Brown ,  Christopher Jones ,  Darrell Boggs

发明人： Gary Brown ,  Christopher Jones ,  Darrell Boggs

IPC分类号： G06F9/00

CPC分类号： G06F9/3017 ,  G06F9/26

摘要： A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level applications can subsequently use, permitting a system manufacturer to create a highly customized and optimized system.

摘要翻译： 包括存储器存储器的微处理器，ISA客户代码程序在被解码成其机器本机微指令之后可被存储到其中。 作为高速缓冲存储器，客户代码存储器不会被驱逐等等。 ISA级代码可以在执行之前指定一个用于存储到客户代码存储中的例程。 因此，客户代码存储库用作可以随后使用ISA级应用程序的预先解码的例程的一次写入的多执行程序库，允许系统制造商创建高度定制和优化的系统。

公开(公告)号：US20060218381A1

公开(公告)日：2006-09-28

申请号：US11090440

申请日：2005-03-24

申请人： Chad Fogg ,  Darrell Boggs ,  Christopher Jones ,  Gary Brown

发明人： Chad Fogg ,  Darrell Boggs ,  Christopher Jones ,  Gary Brown

IPC分类号： G06F9/44

CPC分类号： G06F7/49947 ,  G06F5/01 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30163 ,  G06F9/30167

摘要： A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an encoded immediate which specifies the shift count N. The processor corrects after the addition and shifting for an absent rounding bias added 2N-1. The ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(A+B+C+D . . . +M+2) >>N

摘要翻译： 一种具有包括具有源操作数的指令的架构的处理器，所述处理器从所述源操作数导出操作数值和控制值中的至少一个。 源操作数可以直接指定操作数值或控制值，另一个被隐式指定。 或者，可以从源操作数值隐式指定和派生两者。 操作数值和控制值中的至少一个是隐式的，未指定。 执行加法和右移和舍入的ADDSRN指令，其中源操作数之一是指定移位计数N的编码立即数。处理器在加法和移位之后校正不加舍入偏差，加上2×N 1 。 ADDSRN指令用于加速数字信号处理代码序列，格式为：=（A + B + C + D ... + M + 2）>> N

公开(公告)号：US20060218380A1

公开(公告)日：2006-09-28

申请号：US11090441

申请日：2005-03-24

申请人： Darrell Boggs ,  Chad Fogg ,  Christopher Jones ,  Gary Brown

发明人： Darrell Boggs ,  Chad Fogg ,  Christopher Jones ,  Gary Brown

IPC分类号： G06F9/30

CPC分类号： G06F9/30163 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3885

摘要： A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an immediate which specifies the shift count N and the processor derives a third added 2N−1, and the ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(A+B+C+D . . . +M+2N−1)>>N

摘要翻译： 一种具有包括具有源操作数的指令的架构的处理器，所述处理器从所述源操作数导出操作数值和控制值中的至少一个。 源操作数可以直接指定操作数值或控制值，另一个被隐式指定。 或者，可以从源操作数值隐式指定和派生两者。 操作数值和控制值中的至少一个是隐式的，未指定。 ADDSRN指令执行相加和右移和舍入，其中一个源操作数是指定移位计数N的立即数，并且处理器导出第三个添加的2 N-1，并且ADDSRN 指令用于加速数字信号处理代码序列，格式为<？in-line-formula description =“In-line Formulas”end =“lead”？> dest：=（A + B + C + D ... + M + 2 N-1）>> N <？in-line-formula description =“In-line Formulas”end =“tail”？>

公开(公告)号：US20060095714A1

公开(公告)日：2006-05-04

申请号：US10982662

申请日：2004-11-03

申请人： Darrell Boggs ,  Christopher Jones ,  Gary Brown

发明人： Darrell Boggs ,  Christopher Jones ,  Gary Brown

IPC分类号： G06F15/00

CPC分类号： G06F9/30021 ,  G06F9/3001 ,  G06F9/30036

摘要： A processor ISA instruction which performs a clipping operation forcing a data element to be within a specified range. A SIMD processor ISA instruction which performs a clipping operation upon each data element in a source operand vector.

摘要翻译： 处理器ISA指令，其执行强制数据元素在指定范围内的限幅操作。 SIMD处理器ISA指令，其对源操作数向量中的每个数据元素执行限幅操作。

公开(公告)号：US20060095713A1

公开(公告)日：2006-05-04

申请号：US10982268

申请日：2004-11-03

申请人： Darrell Boggs ,  Christopher Jones ,  Gary Brown

发明人： Darrell Boggs ,  Christopher Jones ,  Gary Brown

IPC分类号： G06F15/00

CPC分类号： G06F9/3001 ,  G06F9/30021 ,  G06F9/30036

摘要： A processor ISA instruction which performs a clipping operation forcing a data element to be within a specified range. A SIMD processor ISA instruction which performs a clipping operation upon each data element in a source operand vector. A SIMD processor ISA instruction which performs clipping upon each data elements in each of a plurality of source operand vectors, and performs picking, rounding, and packing upon the clipped operand vectors to generate a single result vector.

摘要翻译： 处理器ISA指令，其执行强制数据元素在指定范围内的限幅操作。 SIMD处理器ISA指令，其对源操作数向量中的每个数据元素执行限幅操作。 SIMD处理器ISA指令，对多个源操作数向量中的每一个中的每个数据元素执行限制，并且在剪切的操作数向量上执行拾取，舍入和打包以生成单个结果向量。

公开(公告)号：US20060218377A1

公开(公告)日：2006-09-28

申请号：US11090358

申请日：2005-03-24

申请人： Darrell Boggs ,  Chad Fogg ,  Christopher Jones ,  Gary Brown

发明人： Darrell Boggs ,  Chad Fogg ,  Christopher Jones ,  Gary Brown

IPC分类号： G06F9/30

CPC分类号： G06F9/30163 ,  G06F9/30167

摘要： A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified.

摘要翻译： 一种具有包括具有源操作数的指令的架构的处理器，所述处理器从所述源操作数导出操作数值和控制值中的至少一个。 源操作数可以直接指定操作数值或控制值，另一个被隐式指定。 或者，可以从源操作数值隐式指定和派生两者。 操作数值和控制值中的至少一个是隐式的，未指定。

公开(公告)号：US20060036801A1

公开(公告)日：2006-02-16

申请号：US10916747

申请日：2004-08-11

申请人： Christpher Jones ,  Gary Brown ,  Darrell Boggs

发明人： Christpher Jones ,  Gary Brown ,  Darrell Boggs

IPC分类号： G06F12/00

CPC分类号： G06F12/0207

摘要： A register file in which the physical row/column mapping is decoupled from the logical row/column mapping. The physical register file includes R*C N-bit storage elements arranged in R rows and C columns. Each physical row includes an N-bit bus, a log2(C)-bit storage element selection line, and a log2(C)-bit output column selection line. In either a logical row or logical column access, no more than one storage element is selected per physical row and coupled to that row's bus, and each column's vertical bit line is uniquely coupled to one row's bus. The values on the storage element selection lines and on the output column selection lines determines which storage elements are coupled to which vertical bit lines. The width C of the register file, the number of rows R of the register file, and the size N of the fundamental data storage element can be independently changed without affecting the others. The size X of the X*N-bit logical data elements can be changed without changing R, C, N, or the width of the buses. The same addressing logic is used, regardless of data size and regardless of whether the access is logically row-wise or column-wise. Horizontal wire count is minimized by an appropriate logical-to-physical mapping of the storage cells.

摘要翻译： 物理行/列映射与逻辑行/列映射分离的寄存器文件。 物理寄存器文件包括以R行和C列排列的R * C N位存储元件。 每个物理行包括N位总线，对数（2）（C）位存储元件选择行和对数2（C）位输出列选择行 。 在逻辑行或逻辑列访问中，每个物理行选择不超过一个存储元素并耦合到该行的总线，并且每列的垂直位线唯一地耦合到一行总线。 存储元件选择线和输出列选择线上的值确定哪些存储元件被耦合到哪个垂直位线。 寄存器文件的宽度C，寄存器文件的行数R和基本数据存储元件的大小N可以独立地改变而不影响其他。 可以在不改变R，C，N或总线宽度的情况下改变X * N位逻辑数据元素的大小X. 使用相同的寻址逻辑，无论数据大小如何，无论访问是逻辑上是逐行还是逐列。 通过存储单元的适当的逻辑到物理映射最小化水平线数。

公开(公告)号：US08397208B2

公开(公告)日：2013-03-12

申请号：US11849081

申请日：2007-08-31

申请人： Gary Brown ,  Mir Derakhshan ,  Kerstin Baird

发明人： Gary Brown ,  Mir Derakhshan ,  Kerstin Baird

IPC分类号： G06F9/45

CPC分类号： G06F8/71 ,  G06F8/24

摘要： Techniques are provided for baselining across multiple domains. Relationship information that associates a collection of requirement objects with a set of configuration management objects is stored. The collection of requirement objects is defined in a requirement management system for a software product, and the set of configuration management objects is defined in a configuration management system that is operable to manage the development of the software product. A particular requirement object from the collection of requirement objects is determined. Based on the relationship information, one or more configuration management objects that are associated with the particular requirement object are determined. A baseline that includes copies of the one or more configuration management objects is created and stored, where the copies include specific versions of the one or more configuration objects.

摘要翻译： 提供技术用于跨多个域的基线。 将要求对象的集合与一组配置管理对象相关联的关系信息被存储。 要求对象的集合在软件产品的需求管理系统中定义，并且配置管理对象的集合在可操作以管理软件产品的开发的配置管理系统中定义。 确定需求对象集合中的特定需求对象。 基于关系信息，确定与特定要求对象相关联的一个或多个配置管理对象。 创建并存储包含一个或多个配置管理对象的副本的基准，其中副本包含一个或多个配置对象的特定版本。

公开(公告)号：US20080059977A1

公开(公告)日：2008-03-06

申请号：US11849073

申请日：2007-08-31

申请人： Gary Brown ,  Mir Derakhshan ,  Kerstin Baird

发明人： Gary Brown ,  Mir Derakhshan ,  Kerstin Baird

IPC分类号： G06F3/00

CPC分类号： G06F8/71

摘要： Techniques are provided for identifying suspect links between objects from multiple domains. A plurality of links that associates a collection of requirement objects with a set of configuration management objects is stored. The collection of requirement objects is defined in a requirement management system for a software product, and the set of configuration management objects is defined in a configuration management system that is operable to manage the development of the software product. A determination is made that a particular requirement object was changed. In response to determining that the particular requirement object was changed, one or more links of the plurality of links are automatically determined. The one or more links respectively associate one or more configuration management objects, of the set of configuration management objects, with the particular requirement object. The one or more links are then identified as suspect.

摘要翻译： 提供了用于识别来自多个域的对象之间的可疑链接的技术。 存储将要求对象的集合与一组配置管理对象相关联的多个链接。 要求对象的集合在软件产品的需求管理系统中定义，并且配置管理对象的集合在可操作以管理软件产品的开发的配置管理系统中定义。 确定特定需求对象已更改。 响应于确定特定需求对象被改变，多个链接中的一个或多个链接被自动确定。 所述一个或多个链接分别将所述一组配置管理对象中的一个或多个配置管理对象与所述特定需求对象相关联。 一个或多个链接然后被识别为可疑。