A system is provided to aid in the laying out of circuits on a semiconductor wafer, in which a wafer map is automatically generated when entering chip sizes, arrangements and other enterable factors, with the goal to maximize yield probability. The subject system accommodates different chip types and arrangements within a wafer map and addresses edge exclusion, the utilization of chiplets and the accommodation of different centering techniques, including a variety of ways of measuring offsets, while outputting a display of the replicated circuits on the wafer as well as chip count and density, utilizing a portable, tailorable, extendable PC-based program featuring an easy-to-use graphical interface. The software application provides the user with different graphical views customized for the different process areas, such as lithography and dicing, with the application being useful for any semiconductor manufacturing facility, foundry or similar industry that needs to generate wafer maps automatically to maximize yield probability.