发明申请
- 专利标题: Hybrid memory architecture for reduced state sequence estimation (RSSE) techniques
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申请号: US11256182申请日: 2005-10-21
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公开(公告)号: US20060039492A1公开(公告)日: 2006-02-23
- 发明人: Kameran Azadet , Erich Haratsch
- 申请人: Kameran Azadet , Erich Haratsch
- 主分类号: H04L23/02
- IPC分类号: H04L23/02
摘要:
A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture to the trace-back architecture (TBA) or the second register exchange architecture.