发明申请
US20060041849A1 Method and apparatus for reducing redundant data in a layout data structure
有权
用于减少布局数据结构中的冗余数据的方法和装置
- 专利标题: Method and apparatus for reducing redundant data in a layout data structure
- 专利标题(中): 用于减少布局数据结构中的冗余数据的方法和装置
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申请号: US10922982申请日: 2004-08-23
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公开(公告)号: US20060041849A1公开(公告)日: 2006-02-23
- 发明人: Elmehdi Aitnouri , Edward Keyes , Stephen Begg , Val Gont , Dale Mclntyre , Mohammed Ouali , Vyacheslav Zavadsky
- 申请人: Elmehdi Aitnouri , Edward Keyes , Stephen Begg , Val Gont , Dale Mclntyre , Mohammed Ouali , Vyacheslav Zavadsky
- 申请人地址: CA Ottawa K2K 2X2
- 专利权人: Semiconductor Insights Inc.
- 当前专利权人: Semiconductor Insights Inc.
- 当前专利权人地址: CA Ottawa K2K 2X2
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06T1/60
摘要:
The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.
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