公开(公告)号：US08606041B2

公开(公告)日：2013-12-10

申请号：US12029199

申请日：2008-02-11

申请人： Edward Keyes ,  Vyacheslav L. Zavadsky

发明人： Edward Keyes ,  Vyacheslav L. Zavadsky

IPC分类号： G06K9/00 ,  G06K9/36

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： A schematic diagram detailing a circuit that was reverse engineered from a plurality of images taken of the circuit is provided. The schematic diagram includes at least one circuit element that was represented as an object in at least one of the plurality of images, such that signal continuity information was determined through local tracing of connectivity between a first image and a second image of the plurality of images. A method of tracing the connectivity within the plurality of images to produce the schematic diagram is also disclosed.

摘要翻译： 提供了详细描述从电路取得的多个图像中反向工程的电路的示意图。 示意图包括至少一个电路元件，其被表示为多个图像中的至少一个图像中的对象，使得信号连续性信息通过对多个图像的第一图像和第二图像之间的连接性的局部跟踪来确定 。 还公开了一种跟踪多个图像内的连接以产生示意图的方法。

公开(公告)号：US07643665B2

公开(公告)日：2010-01-05

申请号：US10929798

申请日：2004-08-31

申请人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01R31/31704 ,  G01R31/318357 ,  G06T7/74 ,  G06T2207/30148

摘要： The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

摘要翻译： 本发明涉及一种确定IC布局图像中的标准单元的位置的计算上有效的方法。 初始步骤提取并表征图像的兴趣点。 执行可能的标准单元位置的粗略定位，并且基于提取的标准单元的实例与图像中的剩余兴趣点的兴趣点的比较。 在包括粗匹配和精细匹配的可能位置的列表上进行更刚性的比较。 粗匹配导致可能位置的最后一个列表。 精细比赛会在模板和候选名单之间进行比较。 进行进一步的滤波以消除噪声和纹理变化的影响，并且生成结果的统计以实现标准单元在IC布局上的位置。

公开(公告)号：US07580557B2

公开(公告)日：2009-08-25

申请号：US12200968

申请日：2008-08-29

申请人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Val Gont ,  Edward Keyes ,  Jason Abt ,  Stephen Begg

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01R31/31704 ,  G01R31/318357 ,  G06T7/74 ,  G06T2207/30148

摘要： The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

摘要翻译： 本发明涉及一种确定IC布局图像中的标准单元的位置的计算上有效的方法。 初始步骤提取并表征图像的兴趣点。 执行可能的标准单元位置的粗略定位，并且基于提取的标准单元的实例与图像中的剩余兴趣点的兴趣点的比较。 在包括粗匹配和精细匹配的可能位置的列表上进行更刚性的比较。 粗匹配导致可能位置的最后一个列表。 精细比赛会在模板和候选名单之间进行比较。 进行进一步的滤波以消除噪声和纹理变化的影响，并且生成结果的统计以实现标准单元在IC布局上的位置。

公开(公告)号：US20060041849A1

公开(公告)日：2006-02-23

申请号：US10922982

申请日：2004-08-23

申请人： Elmehdi Aitnouri ,  Edward Keyes ,  Stephen Begg ,  Val Gont ,  Dale Mclntyre ,  Mohammed Ouali ,  Vyacheslav Zavadsky

发明人： Elmehdi Aitnouri ,  Edward Keyes ,  Stephen Begg ,  Val Gont ,  Dale Mclntyre ,  Mohammed Ouali ,  Vyacheslav Zavadsky

IPC分类号： G06F17/50 ,  G06T1/60

CPC分类号： G06F17/5072

摘要： The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.

摘要翻译： 根据本发明的方法和装置通过减少互连组内的电冗余互连的数量来减少布局数据结构的数据大小。 电冗余互连是互连组之间的重复互连，这不利于对IC的理解。 因此，可以在布局数据结构中从存储体中删除多个这些互连，只要保留足够的互连以维持银行的电连接性和视觉表示。

公开(公告)号：US20060031792A1

公开(公告)日：2006-02-09

申请号：US10910624

申请日：2004-08-04

申请人： Vyacheslav Zavadsky ,  Elmehdi Aitnouri ,  Edward Keyes ,  Jason Abt ,  Val Gont ,  Stephen Begg

发明人： Vyacheslav Zavadsky ,  Elmehdi Aitnouri ,  Edward Keyes ,  Jason Abt ,  Val Gont ,  Stephen Begg

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm. This algorithm determines the areas of high density where high flow is dictated by the triangle or trapezoid having the lowest current capacity. The areas of high density are flagged as points where short circuits may exist. These flagged points may then be investigated to confirm whether they are short circuits.

摘要翻译： 根据本发明的方法和装置确定在集成电路布局的多边形表示中不正确连接的多边形的位置。 这些不正确连接的多边形导致短路，这通常发生在诸如电源和地面之类的主要信号总线上。 确定短路的确切位置可能是耗时的。 本发明包括将包括每个导电层的多边形表示细分为预定形状（例如三角形或梯形）的步骤。 然后，每个三角形或梯形被转换成节点以开发节点，其中节点彼此直接相连以表示具有与其它形状边缘相邻的边缘的形状。 然后指定相邻节点之间的每个连接的当前容量。 电连接到不正确连接的多边形的两个节点被选择并用作网络流分析算法的参数。 该算法确定了高流量由具有最低电流容量的三角形或梯形决定的高密度区域。 高密度区域被标记为可能存在短路的点。 然后可以调查这些标记点以确认它们是否是短路。

公开(公告)号：US07886258B2

公开(公告)日：2011-02-08

申请号：US12816144

申请日：2010-06-15

申请人： Mohammed Ouali ,  Jason Abt ,  Edward Keyes ,  Vyacheslav Zavadsky

发明人： Mohammed Ouali ,  Jason Abt ,  Edward Keyes ,  Vyacheslav Zavadsky

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06K9/623

摘要： A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure. When different shaped dummy features in the same data structure are encountered, a further reference feature may be selected and the process repeated.

摘要翻译： 描述了从源数据结构中减少电非功能元件（称为虚拟特征）的发生的方法和装置。 源数据结构可以是图像数据，基于向量的数据结构或一些其他数据格式。 检测源数据结构中的虚拟特征，然后删除。 可以通过选择代表性的虚拟特征，将其用作参考图案或多边形并将其与源数据结构中的特征进行比较来检测虚拟特征。 将所选择的参考与比较的步骤包括选择截止相关阈值，以及计算参考和特征之间的相关系数。 基于它们的相关系数和所选择的截止相关阈值之间的比较来选择性地去除特征。 该阈值可能需要更新以去除源数据结构中的所有虚拟特征。 当遇到相同数据结构中的不同形状的虚拟特征时，可以选择另外的参考特征并重复该过程。

公开(公告)号：US20070256037A1

公开(公告)日：2007-11-01

申请号：US11411593

申请日：2006-04-26

申请人： Vyacheslav Zavadsky ,  Edward Keyes ,  Sergei Sourjko ,  Val Gont ,  Stephen Begg ,  Jason Abt

发明人： Vyacheslav Zavadsky ,  Edward Keyes ,  Sergei Sourjko ,  Val Gont ,  Stephen Begg ,  Jason Abt

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： The present invention provides an accurate and efficient method of organizing circuitry from a net-list of an integrated circuit, by the steps of generating a reference pattern; identifying the potential matches in the net-list using inexact graph matching; further analyzing the matches to determine if they match the reference pattern; and organizing the net-list into a hierarchy by replacing the identified instances with higher-level representations.

摘要翻译： 本发明提供一种通过产生参考图案的步骤从集成电路的网络列表组织电路的精确和有效的方法; 使用不精确的图匹配来识别网络列表中的潜在匹配; 进一步分析匹配以确定它们是否匹配参考模式; 并通过用更高级别的表示替换所识别的实例来将网络列表组织成层次结构。

公开(公告)号：US07207018B2

公开(公告)日：2007-04-17

申请号：US10910624

申请日：2004-08-04

申请人： Vyacheslav L. Zavadsky ,  Elmehdi Aitnouri ,  Edward Keyes ,  Jason Abt ,  Val Gont ,  Stephen Begg

发明人： Vyacheslav L. Zavadsky ,  Elmehdi Aitnouri ,  Edward Keyes ,  Jason Abt ,  Val Gont ,  Stephen Begg

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm. This algorithm determines the areas of high density where high flow is dictated by the triangle or trapezoid having the lowest current capacity. The areas of high density are flagged as points where short circuits may exist. These flagged points may then be investigated to confirm whether they are short circuits.

摘要翻译： 根据本发明的方法和装置确定在集成电路布局的多边形表示中不正确连接的多边形的位置。 这些不正确连接的多边形导致短路，这通常发生在诸如电源和地面之类的主要信号总线上。 确定短路的确切位置可能是耗时的。 本发明包括将包括每个导电层的多边形表示细分为预定形状（例如三角形或梯形）的步骤。 然后，每个三角形或梯形被转换成节点以开发节点，其中节点彼此直接相连以表示具有与其它形状边缘相邻的边缘的形状。 然后指定相邻节点之间的每个连接的当前容量。 电连接到不正确连接的多边形的两个节点被选择并用作网络流分析算法的参数。 该算法确定了高流量由具有最低电流容量的三角形或梯形决定的高密度区域。 高密度区域被标记为可能存在短路的点。 然后可以调查这些标记点以确认它们是否是短路。

公开(公告)号：US09141194B1

公开(公告)日：2015-09-22

申请号：US13343652

申请日：2012-01-04

申请人： Edward Keyes ,  Michael Patrick Johnson ,  Thad Starner

发明人： Edward Keyes ,  Michael Patrick Johnson ,  Thad Starner

IPC分类号： G06F3/01

CPC分类号： G06F3/014 ,  G01R33/0029 ,  G01R33/0206 ,  G02B27/017 ,  G02B2027/0138 ,  G02B2027/014 ,  G02B2027/0178 ,  G06F3/011 ,  G06F3/017 ,  G06F3/0346 ,  G06T19/006

摘要： A wearable computing device such as a head-mounted display (HMD) may be equipped with a magnetometer for detecting presence and motion of a hand-wearable magnet (HWM). The HMD may analyze magnetic field measurements of the magnetometer to determine when the HWM moves within a threshold distance of the magnetometer, and may thereafter determine one or more patterns of motion of the HWM based the magnetic field measurements. The HMD may operate in a background detection state in order to determine a background magnetic field strength and to monitor for magnetic disturbances from the HWM. Upon occurrence of a trigger event corresponding to magnetic disturbance above a threshold level, the HMD may transition to operating in a gesture detection state in which it analyzes magnetometer measurements for correspondence with known gestures. Upon recognizing a known gesture, the HMD may carry out one or more actions based on the recognized known gesture.

摘要翻译： 诸如头戴显示器（HMD）的可戴式计算设备可以配备有用于检测手持式可动磁铁（HWM）的存在和运动的磁力计。 HMD可以分析磁力计的磁场测量，以确定HWM何时在磁力计的阈值距离内移动，然后可以基于磁场测量确定HWM的一个或多个运动模式。 HMD可以在背景检测状态下操作，以便确定背景磁场强度并监视来自HWM的磁干扰。 当发生对应于高于阈值水平的磁扰动的触发事件时，HMD可以转换到手势检测状态中的操作，其中它分析磁力计测量值以与已知手势对应。 在识别到已知手势之后，HMD可以基于所识别的已知手势来执行一个或多个动作。

公开(公告)号：US08347262B2

公开(公告)日：2013-01-01

申请号：US12989739

申请日：2008-04-18

申请人： Vyacheslav Zavadsky ,  Edward Keyes ,  Shane Edmonds ,  Alexei Novikov

发明人： Vyacheslav Zavadsky ,  Edward Keyes ,  Shane Edmonds ,  Alexei Novikov

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method, computer-readable medium and system are described for deriving a schematic diagram representative of an integrated circuit (1C) comprising a plurality of circuit elements. In general, the method, computer-readable medium and system are configured to receive as input a working schematic diagram identifying at least some of the circuit elements, and at least one existing schematic diagram from one or more libraries thereof. Based on this input, at least a portion of the working schematic diagram that matches at least a portion of the at least one existing schematic diagram is identified and replaced, thereby forming a revised schematic diagram.

摘要翻译： 描述了一种用于导出代表包括多个电路元件的集成电路（1C）的示意图的方法，计算机可读介质和系统。 通常，该方法，计算机可读介质和系统被配置为接收标识至少一些电路元件的工作原理图以及来自其一个或多个库的至少一个现有示意图。 基于该输入，识别并替换与至少一个现有示意图的至少一部分相匹配的工作示意图的至少一部分，从而形成修改后的示意图。