Invention Application
US20060043558A1 Stacked integrated circuit cascade signaling system and method
审中-公开
堆叠式集成电路级联信号系统及方法
- Patent Title: Stacked integrated circuit cascade signaling system and method
- Patent Title (中): 堆叠式集成电路级联信号系统及方法
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Application No.: US10931828Application Date: 2004-09-01
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Publication No.: US20060043558A1Publication Date: 2006-03-02
- Inventor: James Cady , Russell Rapport , James Wilder
- Applicant: James Cady , Russell Rapport , James Wilder
- Applicant Address: US TX Austin 78757
- Assignee: Staktek Group L.P.
- Current Assignee: Staktek Group L.P.
- Current Assignee Address: US TX Austin 78757
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
Abstract of the DisclosureIntegrated circuits (ICs) are stacked into modules that conserve PCB or other board surface area. The modules provide for lower capacitance memory signaling systems and methods for connecting stacked CSPs in a serial cascade arrangement. In one preferred embodiment, on-die terminations are used selectively to terminate a cascaded series of conductive paths. In another preferred embodiment, a form standard provides a physical form that allows many of the varying package sizes found in a broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.
Information query
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