发明申请
- 专利标题: Dynamic clock frequency adjustment based on processor load
- 专利标题(中): 基于处理器负载的动态时钟频率调整
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申请号: US10931496申请日: 2004-08-31
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公开(公告)号: US20060047987A1公开(公告)日: 2006-03-02
- 发明人: Rajeev Prabhakaran , Jagrut Patel , Martin (Vyungchon) Choe , Kyle Parrington
- 申请人: Rajeev Prabhakaran , Jagrut Patel , Martin (Vyungchon) Choe , Kyle Parrington
- 主分类号: G06F1/30
- IPC分类号: G06F1/30
摘要:
In general, the disclosure is directed to techniques for reducing power consumption within computing devices, such as wireless communication devices. A device dynamically adjusts the CPU clock frequency based on CPU load in order to reduce power consumption. The device monitors the load of the CPU using a number of sample interrupts. The device determines whether to adjust the clock frequency based on the monitored load of the CPU. In general, the device increases the clock frequency when the load of the CPU is high and decreases the clock frequency when the load of the CPU is low.
公开/授权文献
- US07711966B2 Dynamic clock frequency adjustment based on processor load 公开/授权日:2010-05-04
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