发明申请
US20060058973A1 Built-in-self-test (BIST) circuit with digital output for phase locked loops-jitter testing and method thereof
审中-公开
内置自检(BIST)电路,具有锁相环数字输出 - 抖动测试及其方法
- 专利标题: Built-in-self-test (BIST) circuit with digital output for phase locked loops-jitter testing and method thereof
- 专利标题(中): 内置自检(BIST)电路,具有锁相环数字输出 - 抖动测试及其方法
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申请号: US11007350申请日: 2004-12-09
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公开(公告)号: US20060058973A1公开(公告)日: 2006-03-16
- 发明人: Yu-Chen Chen
- 申请人: Yu-Chen Chen
- 专利权人: Ali Corporation
- 当前专利权人: Ali Corporation
- 优先权: TW93127590 20040910
- 主分类号: G01R29/26
- IPC分类号: G01R29/26
摘要:
A built-in-self-testing (BIST) circuit with digital output for phase locked loops-jitter testing and the method thereof are used to solve the problems of difficult processing and test of high frequency signals encountered during test of jitter signal of phase locked loops. The built-in-self-testing (BIST) circuit with digital output for phase locked loops-jitter testing comprises a phase locked loop unit electrically connected with a frequency divide unit. The frequency divide unit is electrically connected with a signal conversion unit. A digital computation unit is electrically connected with the signal conversion unit. A maximum hold circuit is electrically connected with the digital computation unit. After an input signal is provided to and processed by the phase locked loop unit, the maximum hold circuit outputs a self test output signal exhibiting the occurrence situation of jitter signal of the phase locked loop unit.
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