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公开(公告)号：US12130316B2
公开(公告)日：2024-10-29
申请号：US18016159
申请日：2020-07-15
发明人： Kwang Sik Choi
IPC分类号： G01R29/027 , G01R23/165 , G01R29/26 , G01R31/14
CPC分类号： G01R29/027 , G01R23/165 , G01R29/26 , G01R31/14
摘要： There is provided a broadband lossless partial discharge detection and noise removal device which includes: a partial discharge occurrence timing pulse acquiring unit acquiring a generated timing pulse of a partial discharge signal at the beginning of generation of a partial discharge signal; a partial discharge magnitude pulse acquiring unit acquiring a magnitude pulse of the partial discharge signal; a synchronization comparing unit detecting a partial discharge digital signal determined according to whether the generated timing pulse of the partial discharge signal and the magnitude pulse are synchronized; and a partial discharge signal generating unit detecting a partial discharge pulse obtained by converting the detected partial discharge digital signal into an analog signal.
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2.发明授权公开(公告)号：US12089953B1
公开(公告)日：2024-09-17
申请号：US17112629
申请日：2020-12-04
发明人： Ning Guo , Jonathan Reid
CPC分类号： A61B5/6843 , A61B5/313 , A61B5/7221 , G01R27/26 , G01R29/26 , G06F3/015 , A61B2560/0209
摘要： The disclosed computer-implemented method may include (1) sampling an output signal of an amplifier that amplifies a voltage difference between two electrodes, (2) calculating, based on a power spectral density of the output signal, a noise power of the output signal over a predetermined frequency band, (3) estimating an interface impedance of at least one of the two electrodes based on the noise power and a predetermined intrinsic current noise of the amplifier, and (4) performing an operation based at least in part on the estimated interface impedance. Various other methods, systems, and devices are also disclosed.
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公开(公告)号：US20240219442A1
公开(公告)日：2024-07-04
申请号：US18512782
申请日：2023-11-17
发明人： Florian RAMIAN , Kay-Uwe SANDER
CPC分类号： G01R29/26 , G01R31/2837
摘要： A measurement device (10a) for performing measurements with respect to a device under test (13) is provided. Said measurement device (10a) comprises a port (11a) for receiving a signal from the device under test (13), a signal level modification unit (14) for modifying the corresponding level of the signal in order to form a modified signal, the signal level modification unit (14) being operable in at least a first operation mode and a second operation mode being different from the first operation mode, a receiving unit (15) for receiving and digitizing the modified signal in order to a form a digitized modified signal, and a processing unit (16).
The signal level of the first operation mode is set, e.g. by an attenuator of the device, such the signal-to-noise-ratio is high but the receiving unit causes non-linearity effects, and the signal level of the second operation mode is set lower, e.g. by an attenuator of the device, such that the receiving unit causes essentially no non-linearity effects.-
公开(公告)号：US20240204823A1
公开(公告)日：2024-06-20
申请号：US18288053
申请日：2022-05-02
发明人： Peter MANKOWSKI , Willem JAGER , Andrei BUIN , Lucas COELHO , Daniel HAILU , Muhammad IKHLAS
IPC分类号： H04B3/54 , B60R16/023 , B60R16/03 , G01R29/26 , H04L12/40
CPC分类号： H04B3/54 , B60R16/023 , B60R16/03 , G01R29/26 , H04L12/40 , H04L2012/40215
摘要： There are provided methods and systems for operating electric vehicles. One example method includes generating, at a first component of the electric vehicle, a message in a first communication protocol and converting, at a first conversion module associated with the first component, the message into a power line communication protocol to form a first converted message. The method also includes transmitting the first converted message over a power line connecting the first component to a second component of the electric vehicle, and converting, at a second conversion module associated with the second component, the first converted message into a second communication protocol to form a second converted message. The second communication protocol is used by the second component. In addition, the method includes receiving the second converted message at the second component.
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公开(公告)号：US20240201254A1
公开(公告)日：2024-06-20
申请号：US18203024
申请日：2023-05-29
发明人： Hyeon Gwan Oh , Beomsang Yoo
IPC分类号： G01R31/317 , G01R29/26 , H01L21/66 , H01L21/67
CPC分类号： G01R31/31709 , G01R29/26 , H01L21/67253 , H01L22/20
摘要： A jitter analyzing apparatus may include a first delay circuit configured to delay a reference clock to output a first clock, a second delay circuit configured to delay the reference clock to output a second clock having a delay value greater than the first delay circuit, and a test device configured to measure a jitter component of the first and second delay circuits by measuring the first clock and the second clock.
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公开(公告)号：US20230400494A1
公开(公告)日：2023-12-14
申请号：US18232341
申请日：2023-08-09
发明人： Tien-Chien HUANG
IPC分类号： G01R29/26 , H03L7/08 , H03L7/07 , H03K19/0185 , G01R31/317
CPC分类号： G01R29/26 , H03L7/08 , H03L7/07 , H03K19/01855 , G01R31/31709 , G01R29/0276
摘要： A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.
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公开(公告)号：US11815548B2
公开(公告)日：2023-11-14
申请号：US17379940
申请日：2021-07-19
申请人： Tektronix, Inc.
发明人： Charles W. Case , Daniel G. Knierim , Joshua J. O'Brien , Josiah A. Bartlett , Julie A. Campbell
CPC分类号： G01R31/2886 , G01R29/26
摘要： A new test system includes a programmed device having an input port for receiving a signal for testing or measuring on the programmed device, and a reprogrammable test accessory having an output coupled to the input port of the programmed device. The reprogrammable test accessory further includes a test port structured to accept one or more test signals from a Device Under Test (DUT), and a reprogrammable processor. The reprogrammable processor may further include reprogrammable standards and protocols, reprogrammable triggers and margin detection, reprogrammable link training, reprogrammable handshaking, and reprogrammable setup and control facilities for either or both of the DUT and the programmed device.
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公开(公告)号：US11709201B2
公开(公告)日：2023-07-25
申请号：US17009480
申请日：2020-09-01
IPC分类号： G01R31/317 , G01R29/26
CPC分类号： G01R31/31709 , G01R29/26 , G01R31/31725
摘要： A time error vector is determined using pairs of two closest points of input-referred noise data that straddle respective crossing times indicating when a clock signal representation crosses a threshold value, a slew rate of the clock signal representation, and the crossing times. A system filter is applied to the time error vector in the frequency domain. A first RMS value is determined indicating a jitter value present in the filtered time error vector. A raw clock signal time error vector of the clock signal under test is generated, the system filter is applied to the raw clock signal time error vector in the frequency domain, and a second RMS value indicating a jitter content of the filtered raw clock signal time error vector is determined. The second RMS value is corrected using the first RMS value to thereby generate a jitter measurement compensated for input-referred noise.
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公开(公告)号：US20230168291A1
公开(公告)日：2023-06-01
申请号：US17969315
申请日：2022-10-19
发明人： Ankur BAL , Sri Ram GUPTA
CPC分类号： G01R29/26 , H03K3/0315 , H03K3/037
摘要： A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.
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公开(公告)号：US11540763B2
公开(公告)日：2023-01-03
申请号：US16645311
申请日：2017-09-08
发明人： Tongsheng Zhang
摘要： A control method and system for filtering power line interference is disclosed. The control method includes the following steps. First, ECG signals are pre-segmented and rectified; then the sinusoidal frequency, amplitude, and phase of the rectified segmented signals are extracted. These estimated sinusoidal parameters from each recorded channel are weighted by their individual signal to noise ratios before being averaged to achieve the optimal powerline frequency, amplitude, and phase. Based on these optimal sinusoidal parameters, the individual sinusoidal waveform is reconstructed and then is subtracted from the corresponding ECG segment, in order to obtain the clean ECG signals. This method of filtering the powerline interference through removal from recorded signals enables accurate measurement without any ringing effect that could lead to signal distortion issues. Thus this invention solves the ringing problem encountered by traditional notch filter techniques when signal amplitude suddenly changes in a measurement.
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