发明申请
- 专利标题: Latch clock generation circuit and serial-parallel conversion circuit
- 专利标题(中): 锁存时钟发生电路和串并转换电路
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申请号: US11233459申请日: 2005-09-22
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公开(公告)号: US20060066356A1公开(公告)日: 2006-03-30
- 发明人: Tsutomu Murata , Kosaku Hioki
- 申请人: Tsutomu Murata , Kosaku Hioki
- 优先权: JP2004-285800 20040930
- 主分类号: H03K19/00
- IPC分类号: H03K19/00
摘要:
A serial-parallel conversion circuit in which power consumption is reduced is provided by using a latch clock generation circuit including multiple latch signal generation circuits which outputs a latch signal with a period of an integer multiple of that of a system clock signal. Here, the latch signal generation circuit includes a gate circuit which receives a control signal and a feedback signal, and outputs, according to a combination of the received control signal and feedback signal, a latch signal obtained by inverting a pulse corresponding to one clock of the system clock signal, and an output synchronization circuit which holds the latch signal output from the gate circuit and at the same time outputs the latch signal as a control signal supplied to a gate circuit of a latch signal generation circuit of the succeeding stage and a feedback signal supplied to the gate circuit of the self stage.
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