发明申请
- 专利标题: Widening jitter margin for faster input pulse
- 专利标题(中): 抖动裕度越大,输入脉冲越快
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申请号: US11231412申请日: 2005-09-20
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公开(公告)号: US20060066371A1公开(公告)日: 2006-03-30
- 发明人: Hisao Takahashi , Toru Takai
- 申请人: Hisao Takahashi , Toru Takai
- 优先权: JP2004-278568 20040924
- 主分类号: H03H11/26
- IPC分类号: H03H11/26
摘要:
A pulse delay circuit induces lager jitter to faster input reference pulse trains than before. A buffer receives a reference pulse train and provides non-inverted and inverted pulses. Low pass filters (LPF) and comparators receive the non-inverted and inverted pulses from the buffer and provide pulses having delayed leading and trailing edges. Dividers divide the delayed pulses by 2 to produce the respective pulse trains having a half frequency. An XOR gate produces an exclusive OR of the delayed and divided pulse trains to provide a pulse train having delayed leading and/or trailing edges relative to the reference pulse train. If the delays by the LPFs and comparators are changed, the output pulses from the XOR gate have jitter.
公开/授权文献
- US07215168B2 Widening jitter margin for faster input pulse 公开/授权日:2007-05-08