发明申请
- 专利标题： SIMULATION TESTING OF DIGITAL LOGIC CIRCUIT DESIGNS
- 专利标题（中）： 数字逻辑电路设计仿真测试
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申请号： US10904056申请日： 2004-10-21
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公开(公告)号： US20060090149A1公开(公告)日： 2006-04-27
- 发明人: Rafael Blanco , Suzanne Granato , Francis Kampf , Douglas Massey
- 申请人： Rafael Blanco , Suzanne Granato , Francis Kampf , Douglas Massey
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.
公开/授权文献
- US07251794B2 Simulation testing of digital logic circuit designs 公开/授权日：2007-07-31
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