Invention Application
US20060099797A1 Integrated circuits with contemporaneously formed array electrodes and logic interconnects
审中-公开
具有同时形成的阵列电极和逻辑互连的集成电路
- Patent Title: Integrated circuits with contemporaneously formed array electrodes and logic interconnects
- Patent Title (中): 具有同时形成的阵列电极和逻辑互连的集成电路
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Application No.: US11315731Application Date: 2005-12-22
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Publication No.: US20060099797A1Publication Date: 2006-05-11
- Inventor: Mirmajid Seyyedy , Glen Hush , Mark Tuttle , Terry Vollman
- Applicant: Mirmajid Seyyedy , Glen Hush , Mark Tuttle , Terry Vollman
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/336 ; H01L21/8242
Abstract:
The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.
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