A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. Multiplier logic is used to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors, and half adder logic is used to produce from a plurality of most significant bits of the pair of 2n-bit vectors a corresponding plurality of carry and sum bits representing those plurality of most significant bits. Further, exponent determination logic determines a product exponent and also determines if that product exponent correspond to a predetermined exponent value. First adder logic performs a sum operation in order to generate a first result equivalent to the addition of the pair of 2n-bit vectors with an increment value injected at a first predetermined rounding position appropriate for a non-overflow condition, the increment value being either a rounding increment value such that the first result produced is a first rounded result or a logic zero value such that the first result produced is a first unrounded result. The rounding increment value is used unless the exponent determination logic has determined that the product exponent corresponds to the predetermined exponent value in which case the logic value zero is used as the increment value. The first adder logic uses as the m most significant bits of the pair of 2n-bit vectors the corresponding m carry and sum bits, the least significant of the m carry bits being replaced with the increment value prior to the first adder logic performing the first sum operation. The second adder logic performs a second sum operation in order to generate a second rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment value injected at a second predetermined rounding position appropriate for an overflow condition. The second adder logic uses as the m−1 most significant bits of the pair of 2n-bit vectors the corresponding m−1 carry and sum bits, the least significant of the m−1 carry bits being replaced with the rounding increment value prior to the second adder logic performing the second sum operation. The n-bit result is then derived from either the first rounded result, the second rounded result or a predetermined result value.