公开(公告)号：US20060136543A1

公开(公告)日：2006-06-22

申请号：US11017217

申请日：2004-12-21

申请人： David Lutz ,  Christopher Hinds

发明人： David Lutz ,  Christopher Hinds

IPC分类号： G06F7/50

CPC分类号： G06F7/485

摘要： A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first and second operands, and alignment logic operable to align the n-bit significand of the smaller operand with the n-bit significand of the larger operand. First adder logic is then operable to perform a first sum operation in order to generate a first rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first adder logic comprising a single level of adder logic. Further, second adder logic is provided to perform a second sum operation in order to generate a second rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition, the second adder logic also comprising a single level of adder logic. Selector logic is then used to derive the n-bit result from either the first rounded result or the second rounded result.

摘要翻译： 提供了一种数据处理装置和方法，用于添加第一和第二浮点操作数的n位有效值以产生n位结果。 数据处理装置包括可操作以确定第一和第二操作数的较大操作数的确定逻辑，以及可操作以将较小操作数的n位有效位与较大操作数的n位有效位对准的对准逻辑。 第一加法器逻辑然后可操作以执行第一和操作，以便以非冗余形式生成第一舍入结果，该第一舍入结果等同于在对应于非溢出的第一预定舍入位置处注入的舍入增量的对齐有效数的相加 条件，第一加法器逻辑包括单级加法器逻辑。 此外，第二加法器逻辑被提供以执行第二和操作，以便以非冗余形式生成等同于在对应于溢出条件的第二预定舍入位置处注入的舍入增量的对齐有效值的第二舍入结果 ，第二加法器逻辑还包括单级加法器逻辑。 然后，选择器逻辑用于从第一个舍入结果或第二个舍入结果导出n位结果。

公开(公告)号：US20060117081A1

公开(公告)日：2006-06-01

申请号：US11077358

申请日：2005-03-11

申请人： David Lutz ,  Christopher Hinds

发明人： David Lutz ,  Christopher Hinds

IPC分类号： G06F7/52

CPC分类号： G06F7/49963 ,  G06F7/487 ,  G06F7/49915 ,  G06F7/49936

摘要： A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors, and sum logic operable to perform a sum operation to add a first set of bits of each of the pair of 2n-bits vectors. Sticky determination logic is also provided for determining from a second set of bits of each of the pair of 2n-bit vectors a sticky value, and selector logic is then used to derive the n-bit result from the output of the sum logic with reference to the sticky value. The sticky determination logic comprises a half-adder structure operable to generate carry and sum vectors from a negated version of the second set of bits of each the pair of 2n-bit vectors, and combination logic for performing a logical XOR operation on the carry and sum vectors with the least significant carry bit set to a logic one value. The sticky value can then be derived from the output of the combination logic. This provides a particularly efficient technique for determining the sticky value without awaiting the production of the final product in non-redundant form.

公开(公告)号：US20070050434A1

公开(公告)日：2007-03-01

申请号：US11211087

申请日：2005-08-25

申请人： David Lutz ,  Christopher Hinds

发明人： David Lutz ,  Christopher Hinds

IPC分类号： G06F15/00

CPC分类号： G06F7/49936 ,  G06F5/01

摘要： A data processing apparatus and method are provided for normalizing a data value to produce a result value. The data processing apparatus includes prediction logic for generating a shift indication based on a prediction of the number of bit positions by which the data value needs to be shifted in order to normalize the data value. Further, normalizer logic is used to apply a shift operation to the data value based on the shift indication. In addition, correction logic is operable in parallel with the normalizer logic to determine from the data value and a least significant bit of the shift indication whether the shift indication has correctly predicted the number of bit positions by which the data value needs to be shifted in order to normalize the data value, or whether instead the prediction is incorrect, and to generate an output signal dependent on that determination. Shift logic is then used, if the output signal indicates that the prediction is incorrect, to apply a correction shift such that the result value is the normalized data value.

摘要翻译： 提供了一种用于对数据值进行归一化以产生结果值的数据处理装置和方法。 数据处理装置包括用于基于需要移动数据值的比特位置的数量的预测来生成移位指示的预测逻辑，以便对数据值进行归一化。 此外，归一化器逻辑用于基于移位指示对数据值应用移位操作。 此外，校正逻辑可与归一化器逻辑并行操作，以根据数据值和移位指示的最低有效位来确定移位指示是否正确地预测了数据值需要被移位的位位置的数量 为了规范化数据值，或者相​​反，预测是不正确的，并且根据该确定产生输出信号。 然后如果输出信号指示预测不正确，则使用移位逻辑来应用校正偏移，使得结果值是归一化数据值。

公开(公告)号：US20050210086A1

公开(公告)日：2005-09-22

申请号：US10803162

申请日：2004-03-18

申请人： David Lutz ,  Christopher Hinds

发明人： David Lutz ,  Christopher Hinds

IPC分类号： G06F7/00 ,  G06F7/544

CPC分类号： G06F7/544 ,  G06F2207/5442

摘要： The present invention provides a data processing apparatus and method for computing an absolute difference between portions of first and second data elements. The data processing apparatus comprises processing logic operable to perform a data processing operation on first and second data elements, the processing logic comprising comparison logic operable to compare at least a part of the first and second data elements in order to determine which of the first and second data elements is a larger data element. The comparison logic is operable to produce a comparison result which has a first value if the first data element is the larger data element and a second value if the second data element is the larger data element. The processing logic further comprises absolute difference logic operable to compute an absolute difference between a portion of the first data element and a portion of the second data element. The absolute difference logic comprises adder logic operable to invert one of the portions to produce an inverted data element portion, and to add the inverted data element portion to the other of the portions and to the comparison result received from the comparison logic in order to produce an intermediate result. Further, the absolute difference logic comprises output logic operable to generate an inverted version of the intermediate result and to output as the absolute difference either the intermediate result or the inverted version of the intermediate result dependent on the comparison result. Through use of the present invention, an absolute difference can be computed without the need to provide logic to swap the ordering of the first and second data element portions prior to the addition dependent on the result of the comparison. Accordingly, a significant improvement in speed of determination of the absolute difference can be realised.

摘要翻译： 本发明提供了一种用于计算第一和第二数据元素的部分之间的绝对差的数据处理装置和方法。 数据处理装置包括可操作以对第一和第二数据元素执行数据处理操作的处理逻辑，所述处理逻辑包括比较逻辑，其可操作以比较所述第一和第二数据元素的至少一部分，以便确定所述第一和第二数据元素中的哪一个 第二数据元素是较大的数据元素。 比较逻辑可操作以产生如果第一数据元素是较大数据元素则具有第一值的比较结果，以及如果第二数据元素是较大数据元素则产生第二值。 处理逻辑还包括绝对差分逻辑，可操作以计算第一数据元素的一部分与第二数据元素的一部分之间的绝对差。 绝对差异逻辑包括加法器逻辑，其可操作以反转部分中的一个以产生反相数据元素部分，并将反相数据元素部分添加到另一部分以及从比较逻辑接收到的比较结果，以产生 中间结果。 此外，绝对差分逻辑包括可操作以产生中间结果的反转版本的输出逻辑，并且根据比较结果输出中间结果的中间结果或反向版本作为绝对差。 通过使用本发明，可以计算出绝对差异，而不需要根据比较结果提供在加法之前交换第一和第二数据元素部分的顺序的逻辑。 因此，可以实现确定绝对差的速度的显着改善。

公开(公告)号：US20050125640A1

公开(公告)日：2005-06-09

申请号：US10889318

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

发明人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/345 ,  G06F9/38 ,  G06F15/80

CPC分类号： G06F9/3887 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3822 ,  G06F9/3885

摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is operation to arrange the plurality of data elements as they are moved such that data elements of different components are stored in different specified registers within the chosen lane whilst in memory the data elements are stored as the structure.

摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以并行地执行对至少一个寄存器中的并行处理的不同通道的多个数据元素的数据处理操作。 提供了访问逻辑，其响应于单个访问指令，以在指定寄存器中的所选择的一个通道中移动多个数据元素，以及在具有结构格式的存储器内的结构，所述结构格式具有多个组件。 单个访问指令标识结构格式中的组件的数量，并且访问逻辑是在移动多个数据元素时排列多个数据元素的操作，使得不同组件的数据元素存储在所选择的通道内的不同指定的寄存器中，同时 存储数据元素作为结构存储。

公开(公告)号：US20060206556A1

公开(公告)日：2006-09-14

申请号：US11078699

申请日：2005-03-14

申请人： David Lutz ,  Christopher Hinds

发明人： David Lutz ,  Christopher Hinds

IPC分类号： G06F7/50

CPC分类号： G06F7/485 ,  G06F7/49936 ,  G06F7/49963 ,  G06F2207/3884

摘要： A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floating point operands is the larger operand. First adder logic is used, if predetermined criteria exists, to perform an addition of the n-bit significands of the first and second floating point operands to produce the sum value, whilst second adder logic is used, if the predetermined criteria does not exist, to perform that addition. Result logic can then derive the n-bit result from either an output of the first adder logic or an output of the second adder logic. If the addition is a like-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require an effective 1-bit right shift to normalise the sum value, whereas if the addition is an unlike-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require at least an effective 1-bit left shift to normalise the sum value.

摘要翻译： 提供了一种数据处理装置和方法，用于添加第一和第二浮点操作数的n位有效值以产生n位结果。 数据处理装置包括用于确定第一和第二浮点操作数中的哪一个是较大操作数的确定逻辑。 如果存在预定标准，则使用第一加法器逻辑来执行第一和第二浮点操作数的n比特有效值的相加以产生和值，同时使用第二加法器逻辑，如果不存在预定标准， 执行该添加。 然后，结果逻辑可以从第一加法器逻辑的输出或第二加法器逻辑的输出导出n位结果。 如果加法是类似签名的加法，则对于由第一加法器逻辑产生的和值将要求有效的1位右移以标准化和值的一组情况，确定预定标准存在，而如果 另外是一个不同签名的加法，对于由第一加法器逻辑产生的和值将要求至少一个有效的1位左移以归一化和值的情况，确定预定准则存在。

公开(公告)号：US20050125641A1

公开(公告)日：2005-06-09

申请号：US10889367

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

发明人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/00

CPC分类号： G06F9/30167 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30145

摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以对在至少一个寄存器中访问的多个数据元素并行地执行数据处理操作。 访问逻辑可操作以响应于单个访问指令来移动指定寄存器之间的多个数据元素和其中数据元素被存储为具有结构格式的结构的阵列的连续存储块，所述结构格式具有多个 组件。 单个访问指令标识结构格式的组件的数量，并且访问逻辑还可用于在移动多个数据元素时重新排列多个数据元素，使得每个指定的寄存器存储一个组件的数据元素，而在存储器中数据元素是 存储为结构数组。

公开(公告)号：US20060184594A1

公开(公告)日：2006-08-17

申请号：US11058421

申请日：2005-02-16

申请人： David Lutz ,  Christopher Hinds ,  Dominic Symes ,  Simon Ford

发明人： David Lutz ,  Christopher Hinds ,  Dominic Symes ,  Simon Ford

IPC分类号： G06F15/00

CPC分类号： G06F7/535 ,  G06F9/30014 ,  G06F9/3004 ,  G06F2207/3824 ,  G06F2207/5354 ,  G06F2207/5355 ,  G06F2207/5356

摘要： The present invention provides a data processing apparatus and method for generating an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data processing apparatus comprises processing logic for executing instructions to perform data processing operations on data, and a lookup table referenced by the processing logic during generation of the initial estimate of the result value. The processing logic is responsive to an estimate instruction to reference the lookup table to generate, dependent on a modified input value that is within a predetermined range of values, a table output value. For a particular modified input value, the same table output value is generated irrespective of whether the input value is a fixed point value or a floating point value. The initial estimate of the result value is then derivable from the table output value. This provides a particularly efficient technique for performing the initial estimate generation within a data processing apparatus where the reciprocal operation may be performed on either fixed point values or floating point values.

摘要翻译： 本发明提供了一种数据处理装置和方法，用于产生通过对输入值执行倒数操作而产生的结果值的初始估计。 输入值和结果值是固定点值或浮点值。 该数据处理装置包括执行用于对数据执行数据处理操作的指令的处理逻辑，以及在生成结果值的初始估计期间由处理逻辑引用的查找表。 处理逻辑响应于估计指令以引用查找表，以根据在预定范围内的修改的输入值来生成表输出值。 对于特定的修改输入值，无论输入值是固定点值还是浮点值，都会生成相同的表格输出值。 结果值的初始估计值可从表输出值推导出来。 这提供了用于在数据处理装置中执行初始估计生成的特别有效的技术，其中可以对固定点值或浮点值执行倒数操作。

公开(公告)号：US20060117082A1

公开(公告)日：2006-06-01

申请号：US11081833

申请日：2005-03-17

申请人： David Lutz ,  Christopher Hinds

发明人： David Lutz ,  Christopher Hinds

IPC分类号： G06F7/52

CPC分类号： G06F7/49963 ,  G06F7/487 ,  G06F7/49915 ,  G06F7/49936

摘要： A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. Multiplier logic is used to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors, and half adder logic is used to produce from a plurality of most significant bits of the pair of 2n-bit vectors a corresponding plurality of carry and sum bits representing those plurality of most significant bits. Further, exponent determination logic determines a product exponent and also determines if that product exponent correspond to a predetermined exponent value. First adder logic performs a sum operation in order to generate a first result equivalent to the addition of the pair of 2n-bit vectors with an increment value injected at a first predetermined rounding position appropriate for a non-overflow condition, the increment value being either a rounding increment value such that the first result produced is a first rounded result or a logic zero value such that the first result produced is a first unrounded result. The rounding increment value is used unless the exponent determination logic has determined that the product exponent corresponds to the predetermined exponent value in which case the logic value zero is used as the increment value. The first adder logic uses as the m most significant bits of the pair of 2n-bit vectors the corresponding m carry and sum bits, the least significant of the m carry bits being replaced with the increment value prior to the first adder logic performing the first sum operation. The second adder logic performs a second sum operation in order to generate a second rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment value injected at a second predetermined rounding position appropriate for an overflow condition. The second adder logic uses as the m−1 most significant bits of the pair of 2n-bit vectors the corresponding m−1 carry and sum bits, the least significant of the m−1 carry bits being replaced with the rounding increment value prior to the second adder logic performing the second sum operation. The n-bit result is then derived from either the first rounded result, the second rounded result or a predetermined result value.

公开(公告)号：US20060117080A1

公开(公告)日：2006-06-01

申请号：US10999154

申请日：2004-11-30

申请人： David Lutz ,  Christopher Hinds

发明人： David Lutz ,  Christopher Hinds

IPC分类号： G06F7/52

CPC分类号： G06F7/487 ,  G06F7/49915 ,  G06F7/49936 ,  G06F7/49963

摘要： A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. Half adder logic is then arranged to produce a plurality of carry and sum bits representing a corresponding plurality of most significant bits of the pair of 2n-bit vectors. The first adder logic then performs a first sum operation in order to generate a first rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition. To achieve this, the first adder logic uses as the m most significant bits of the pair of 2n-bit vectors the corresponding m carry and sum bits, the least significant of the m carry bits being replaced with a rounding increment value prior to the first adder logic performing the first sum operation. Second adder logic is arranged to perform a second sum operation in order to generate a second rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition. To achieve this, the second adder logic uses as the m-1 most significant bits of the pair of 2n-bit vectors the corresponding m−1 carry and sum bits, with the least significant of the m−1 carry bits being replaced with the rounding increment value prior to the second adder logic performing the second sum operation. The required n-bit result is then derived from either the first rounded result or the second rounded result. The data processing apparatus takes advantage of a property of the half adder form to enable a rounding increment value to be injected prior to performance of the first and second sum operations without requiring full adders to be used to inject the rounding increment value.