发明申请
US20060121711A1 Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions
失效
用于形成具有特定尺寸的栅极侧壁间隔物的半导体装置的方法
- 专利标题: Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions
- 专利标题(中): 用于形成具有特定尺寸的栅极侧壁间隔物的半导体装置的方法
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申请号: US11002586申请日: 2004-12-03
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公开(公告)号: US20060121711A1公开(公告)日: 2006-06-08
- 发明人: Mark Kelling , Douglas Bonser , Srikanteswara Dakshina-Murthy , Asuka Nomura
- 申请人: Mark Kelling , Douglas Bonser , Srikanteswara Dakshina-Murthy , Asuka Nomura
- 专利权人: ADVANCED MICRO DEVICES, INC.
- 当前专利权人: ADVANCED MICRO DEVICES, INC.
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
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